DMI COLLEGE OF ENGINEERING

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1 DMI COLLEGE OF ENGINEERING PALANCHUR CHENNAI - 6 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING LABORATORY MANUAL SUB CODE : EC6 SUBJECT TITLE : ANALOG AND DIGITAL CIRCUITS LABORATORY SEMESTER : III YEAR : II DEPARTMENT : ELECTRONICS AND COMMUNICATION ENGINEERING

2 EC6-Analog and Digital Circuits Lab Vision of the Department To develop committed and competent technologists in electronics and communication engineering to be on par with global standards coupled with cultivating the innovations and ethical values. Mission of the Department: DM : To be a centre of ecellence in teaching learning process promoting active learning with critical thinking. DM : To strengthen the student s core domain and to sustain collaborative industry interaction with internship and incorporating entrepreneur skills. DM : To prepare the students for higher education and research oriented activities imbibed with ethical values for addressing the social need. PROGRAM EDUCATIONAL OBJECTIVES (PEOs): PEO. CORE COMPETENCY WITH EMPLOYABILITY SKILLS: Building on fundamental knowledge, to analyze, design and implement electronic circuits and systems in Electronics and Communication Engineering by applying knowledge of mathematics and science or in closely related fields with employability skills. PEO. PROMOTE HIGHER EDUCATION AND RESEARCH AND DEVELOPMENT: To develop the ability to demonstrate technical competence and innovation that initiates interest for higher studies and research. PEO. INCULCATING ENTREPRENEUR SKILLS: To motivate the students to become Entrepreneurs in multidisciplinary domain by adapting to the latest trends in technology catering the social needs. PEO4. ETHICAL PROFESSIONALISM: To develop the graduates to attain professional ecellence with ethical attitude, communication skills, team work and develop solutions to the problems and eercise their capabilities.

3 EC6-Analog and Digital Circuits Lab PROGRAM OUTCOMES (POs) The Program Outcomes (POs) are described as.. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering fundamentals and an engineering specialization to the solution of comple engineering problems.. Problem Analysis: Identify, formulate, review research literature, and analyze comple engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.. Design / Development of solutions: Design solutions for comple engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations. 4. Conduct investigations of comple problems: Use research-based knowledge and research methods including design of eperiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions. 5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modelling to comple engineering activities with an understanding of the limitations. 6. The engineer and society: Apply reasoning informed by the contetual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice. 7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal and environmental contets, and demonstrate the knowledge of, and need for sustainable development. 8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice. 9. Individual and team work: Function effectively as an individual and as a member or leader in diverse teams, and in multidisciplinary settings.

4 EC6-Analog and Digital Circuits Lab. Communication: Communicate effectively on comple engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions.. Project management and finance: Demonstrate knowledge and understanding of the engineering management principles and apply these to one s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments.. Life-long learning: Recognize the need for and have the preparation and ability to engage in independent and lifelong learning in the broadest contet of technological change. PROGRAM SPECIFIC OUTCOMES (PSOs): PSO. Analyze and design the analog and digital circuits or systems for a given specification and function. PSO. Implement functional blocks of hardware-software co-designs for signal processing and communication applications. PSO. Design, develop and test electronic and embedded systems for applications with real time constraint and to develop managerial skills with ethical behavior to work in a sustainable environment. 4

5 EC6-Analog and Digital Circuits Lab INSTRUCTIONS TO STUDENTS FOR WRITING THE RECORD In the record, the inde page should be filled properly by writing the corresponding eperiment number, eperiment name, date on which it was done and the page number. On the right side page of the record following has to be written:. Title: The title of the eperiment should be written in the page in capital letters. In the left top margin, eperiment number and date should be written.. Aim: The purpose of the eperiment should be written clearly.. Apparatus/Tools/Equipments/Components used: A list of the Apparatus/Tools/ Equipments/ Components used for doing the eperiment should be entered. 4. Theory: Simple working of the circuit/eperimental set up/algorithm should be written. 5. Procedure: Steps for doing the eperiment and recording the readings should be briefly described(flow chart/ Circuit Diagrams / programs in the case of computer/processor related eperiments) 6. Results: The results of the eperiment must be summarized in writing and should be fulfilling the aim. On the Left side page of the record following has to be recorded: a) Circuit/Program: Neatly drawn circuit diagrams for the eperimental set up. b) Design: The design of the circuit components for the eperimental set up for selecting the components should be clearly shown if necessary. Observations: i. Data should be clearly recorded using Tabular Columns. ii. Unit of the observed data should be clearly mentioned iii. Relevant calculations should be shown. If repetitive calculations are needed, only show a sample calculation and summarize the others in a table. 5

6 EC6-Analog and Digital Circuits Lab SYLLABUS LIST OF EXPERIMENTS LIST OF ANALOG EXPERIMENTS: (GROUP A). Frequency Response of CE / CB / CC amplifier. Frequency response of CS Amplifiers. Darlington Amplifier 4. Differential Amplifiers- Transfer characteristic, CMRR Measurement 5. Cascode / Cascade amplifier 6. Determination of bandwidth of single stage and multistage amplifiers 7. Spice Simulation of Common Emitter and Common Source amplifiers LIST OF DIGITAL EXPERIMENTS :(GROUP B) 8. Design and Implementation of Adder and Subtractor. 9. Design and implementation of code converters using logic gates (i) BCD to ecess- code and vice versa (ii) Binary to gray and vice-versa. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 748. Design and implementation of Multipleer and De-multipleer using logic gates. Design and implementation of encoder and decoder using logic gates. Construction and verification of 4 bit ripple counter and Mod- / Mod- Ripple counters 4. Design and implementation of -bit synchronous up/down counter 5. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops TOTAL : 45 PERIODS 6

7 EC6-Analog and Digital Circuits Lab Subject code/ name: EC6 / Analog & Digital Circuits Laboratory Course code: C7 Regulation: Semester: III Course outcomes: C7. Design amplifiers, Rectifiers. C7. Analyze the frequency response of amplifiers. C7. Analyze low & high frequencies of BJT & MOSFET amplifiers. C7.4 To implement Code converters, Adder, Subtractor and logic gates. C7.5 Spice simulation of analog and Digital circuits CO PO, PSO Mappings Course Code Program Outcomes and Course PSO CO name EC64 C Analog C &Digital C circuits C Laboratory C Average

8 EC6-Analog and Digital Circuits Lab EC6 ANALOG AND DIGITAL CIRCUITS LABORATORY CONTENTS Sl. No..a.b.c 4 Name of the Eperiment Page No. ANALOG EXPERIMENTS Frequency Response of CE amplifier Frequency Response of CB amplifier Frequency Response of CC amplifier Frequency response of CS Amplifiers Darlington Amplifier Differential Amplifiers- Transfer characteristic, CMRR Measurement 5.a 5.b Cascade amplifier Cascode amplifier 6.a 6.b Determination of bandwidth of single stage amplifiers Determination of bandwidth of multistage amplifiers 7.a 7.b Spice Simulation of Common Emitter amplifiers Spice Simulation of Common Source amplifiers DIGITAL EXPERIMENTS Design and Implementation of Adder and Subtractor using logic gates Design and Implementation of Code Converters (i) BCD to ecess- code and vice-versa (ii) Binary to gray and vice-versa Design and Implementation of 4 Bit Binary Adder/ Subtractor and BCD Adder Design and Implementation of Multipleer and De-Multipleer Design and Implementation of Encoder and Decoder Construction and Verification of 4 Bit Ripple Counter and Mod- / Mod- Design and Implementation of -Bit Synchronous Up/Down Counter Design and Implementation of Shift Registers ADDITIONAL EXPERIMENTS BEYOND THE SYLLABUS 6 Analysis Of Cascade Amplifier Using Spice 8

9 EC6-Analog and Digital Circuits Lab EXP NO:.a FREQUENCY RESPONSE OF COMMON EMMITER AMPLIFIER DATE: AIM: To construct a Common Emitter amplifier circuit and to plot the frequency response characteristics. APPARATUS REQUIRED: S.N o Name Range Quantity Transistor Resistor Capacitor Function Generator CRO Regulated power Supply Bread Board Connecting Wires BC 7 k,6,.4k, 9,.5k,k μf,47μf (-)MHz MHz (-)V, Few THEORY: The CE amplifier provides high gain and wide frequency response. The emitter lead is common to both the input and output circuits are grounded. The emitter base junction is at forward biased.the collector current is controlled by the base current rather than the emitter current. The input signal is applied to the base terminal of the transistor and amplified output taken across collector terminal. A very small change in base current produces a much larger change in collector current. When the positive is fed to input circuit it opposes forward bias of the circuit which cause the collector current to decrease, it decreases the more negative. Thus when input cycle varies through a negative half cycle, increases the forward bias of the circuit, which causes the collector current increases.thus the output signal in CE is out of phase with the input signal. 9

10 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM: Common Emitter Amplifier TABULAR COLUMN: Keep the input voltage constant, Vin = Frequency Output Voltage S.No Av = V/ Vin (Hz) Gain = log Av (db) V(volts)

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12 EC6-Analog and Digital Circuits Lab

13 EC6-Analog and Digital Circuits Lab PROCEDURE:. Select different components and place them in the grid.. For calculating the voltage gain the input voltage of 5mv (p-p) amplitude and KHz frequency is applied, then the circuit is simulated and output voltage is noted.. The voltage gain is calculated by using the epression 4. For plotting frequency response, the input voltage is kept constant at 5mv (p-p) and frequency is varied. 5. Note down the output voltage for each frequency. 6. All readings are tabulated and Av in db is calculated using the formula 7. A graph is drawn by taking frequency on X-ais and gain in db on Y-ais on a Semi log graph sheet. RESULT : The frequency response of common emitter amplifier is tabulated and bandwidth is calculated. Gain = Bandwidth = GBP = VIVA QUESTIONS:. What is the phase difference between input and output waveforms of CE amplifier?. What type of biasing is used in the given circuit?. If the given transistor is replaced by P-N-P, Can we get the output or not? 4. What is the effect of emitter bypass capacitor on frequency response? 5. What is the effect of coupling capacitor? 6. What is the region of transistor so that it operates as an amplifier? 7. Draw the h-parameter model of CE amplifier. 8. How does transistor acts as an amplifier.

14 EC6-Analog and Digital Circuits Lab EXP NO:.b FREQUENCY RESPONSE OF COMMON BASE AMPLIFIER DATE: AIM: To construct a common base amplifier circuit and to plot the frequency response characteristics. APPARATUS REQUIRED: S.N Name o.. Transistor. Resistor Capacitor Function Generator CRO Regulated power supply Bread Board Connecting wires Range Quantity BC 7 IK,8.6K,8K,.5K,5K μf (-)MHz MHz (-)V,,,, Few THEORY: In this amplifier configuration, base of the transistor is at AC ground and input is applied at the low input impedance emitter node. This amplifier achieves the high gain and input impedance of the amplifier is very low. Common-base transistor amplifiers are so-called because the input and output voltage points share the base lead of the transistor in common with each other, not considering any power supplies. The current gain of a common-base amplifier is always less than. The voltage gain is a function of input and output resistances, and also the internal resistance of the emitter-base junction, which is subject to change with variations in DC bias voltage. Suffice to say that the voltage gain of a common-base amplifier can be very high. The ratio of a transistor's collector current to emitter current is called α. The value for any transistor is always less than unity, or in other words, less than. 4

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16 EC6-Analog and Digital Circuits Lab 6

17 EC6-Analog and Digital Circuits Lab PROCEDURE:. Connect the circuit as per the circuit diagram.. Set Vi =5 mv, using the signal generator.. Keeping the input voltage constant, vary the frequency from Hz to M Hz in regular steps and note down the corresponding output voltage. Plot the graph; Gain (db) Vs Frequency (Hz). RESULT: Thus, the Common base amplifier was and the frequency response curve is plotted. Gain = Bandwidth = GBP = VIVA QUESTIONS:. What will be the input &output impedance of common Base amplifier?. Write some applications of common base amplifier.. What is the current amplification factor of common base amplifier? 7

18 EC6-Analog and Digital Circuits Lab EXP NO:.c FREQUENCY RESPONSE OF COMMON COLLECTOR AMPLIFIER DATE: AIM: To construct a common collector amplifier circuit and to plot the frequency response characteristics. APPARATUS REQUIRED: S.No... Name Transistor Resistor. 4. Capacitor Function Generator CRO MHz Regulated (-)V power supply Bread Board Connecting Wires Range BC 7 k,5k,64,68 IμF (-)MHz Quantity Few THEORY: The d.c biasing in common collector is provided by R, R and RE.The load resistance is capacitor coupled to the emitter terminal of the transistor. When a signal is applied to the base of the transistor, V B is increased and decreased as the signal goes positive and negative, respectively. Considering V BE is constant the variation in the VB appears at the emitter and emitter voltage VE will vary same as base voltage VB. Since the emitter is output terminal, it can be noted that the output voltage from a common collector circuit is the same as its input voltage. Hence the common collector circuit is also known as an emitter follower. 8

19 EC6-Analog and Digital Circuits Lab 9

20 EC6-Analog and Digital Circuits Lab PRACTICAL CALCULATIONS:

21 EC6-Analog and Digital Circuits Lab PROCEDURE:. Connect the circuit as per the circuit diagram.. Set Vi =5 mv, using the signal generator.. Keeping the input voltage constant, vary the frequency from Hz to M Hz in regular steps and note down the corresponding output voltage. 4. Plot the graph; Gain (db) Vs Frequency (Hz). RESULT: Thus, the Common collector amplifier was and the frequency response curve is plotted. Gain = Bandwidth = GBP = VIVA QUESTIONS:. Why the common collector amplifier is also called an emitter follower. What is the need for coupling capacitors?. What will be the input &output impedance of common collector amplifier? 4. Write some applications of common collector amplifier. 5. What is the current amplification factor of common collector amplifier?

22 EC6-Analog and Digital Circuits Lab EXP NO: DATE: FREQUENCY RESPONSE OF COMMON SOURCE AMPLIFIER AIM : To design and simulate the frequency response of common source amplifier APPARATUS REQUIRED: S.No... Name Transistor Resistor Capacitor Function Generator CRO Regulated power supply Bread Board Connecting Wires 7. 8 Range N547.5K,M,K,.μF,μF (-)MHz MHz (-)V Quantity, Few THEORY: A weak signal is applied between gate and source and output is obtained at drain. For the proper operation of FET, gate must be reverse biased. A small change in reverse bias on the gate produces a large drain current. This fact makes FET capable of raising the strength of a weak signal. The gain of the common source FET amplifier is very high which is greater than unity.

23 EC6-Analog and Digital Circuits Lab FREQUENCY RESPONSE:

24 EC6-Analog and Digital Circuits Lab PRACTICAL CALCULATIONS: 4

25 EC6-Analog and Digital Circuits Lab PROCEDURE:. Select different components and place them in the grid.. For calculating the voltage gain the input voltage of.v(p-p) amplitude and KHz frequency is applied, then the circuit is simulated and output voltage is noted.. The voltage gain is calculated by using the epression Av = Vo / Vi 4. For plotting frequency response the input voltage is kept constant at.v(p-p) and frequency is varied. 5. Note down the output voltage for each frequency. 6. All readings are tabulated and Av in db is calculated using Log Vo / Vi. 7. A graph is drawn by taking frequency on X-ais and gain in db on Y-ais on a Semi-log graph sheet. RESULT: The frequency response of common source amplifier was studied and Gain = Bandwidth = GBP = VIVA QUESTIONS:. How does FET acts as an amplifier?. What are the parameters of a FET?. What is an amplification factor? 4. Draw the h-parameter model of the FET. 5. What are the advantages of FET over BJT? 6. What is the region of FET so that it acts as an amplifier? 7. What are the differences between JFET and MOSFET? 8. What type of biasing is used in the given circuit? 5

26 EC6-Analog and Digital Circuits Lab EXP NO: DATE: DARLINGTON AMPLIFIER USING BJT AIM: To construct a Darlington current amplifier circuit and to plot the frequency response characteristics. APPARATUS REQUIRED: S.No... Name Transistor Resistor. 4. Capacitor Function Generator CRO MHz Regulated (-)V power supply Bread Board Connecting Wires Range BC 7 K.68,5K,6K μf (-)MHz Quantity Few THEORY: In Darlington connection of transistors, emitter of the first transistor is directly connected to the base of the second transistor.because of direct coupling dc output current of the first stage is (+hfe )Ib.If Darlington connection for n transistor is considered, then due to direct coupling the dc output current foe last stage is (+hfe ) n times Ib.Due to very large amplification factor even two stage Darlington connection has large output current and output stage may have to be a power stage. As the power amplifiers are not used in the amplifier circuits it is not possible to use more than two transistors in the Darlington connection. In Darlington transistor connection, the leakage current of the first transistor is amplified by the second transistor and overall leakage current may be high, Which is not desired. 6

27 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM: Here Ci =CO =Μf 7

28 EC6-Analog and Digital Circuits Lab 8

29 EC6-Analog and Digital Circuits Lab PROCEDURE:. Connect the circuit as per the circuit diagram.. Set Vi =5 mv, using the signal generator.. Keeping the input voltage constant, vary the frequency from Hz to M Hz in regular steps and note down the corresponding output voltage. 4. Plot the graph; Gain (db) vs Frequency (Hz). 5. Calculate the bandwidth from the graph. CALCULATION Amplification factor β =IC / IB = Amplification factor β =IC / IB = RESULT: Thus, the Darlington current amplifier was constructed and the frequency response curve is plotted.. a) Amplification factor β = b) Amplification factor β = c) Total current gain β β = VIVA QUESTIONS:. What is meant by Darlington pair?. How many transistors are used to construct a Darlington amplifier circuit?. What is the advantage of Darlington amplifier circuit? 4. Write some applications of Darlington amplifier. 9

30 EC6-Analog and Digital Circuits Lab EXP NO: 4 DATE: DIFFERENTIAL AMPLIFIER USING BJT AIM To construct a differential amplifier using BJT and to determine the dc collector current of individual transistors and also to calculate the CMRR. APPARATUS REQUIRED: S.No... Name Transistor Resistor. Regulated power supply Function (-) MHz Generator CRO MHz Bread Board Connecting Wires Range BC7 4.7kΩ, kω (-)V Quantity, Few THEORY: The differential amplifier is a basic stage of an integrated operational amplifier. It is used to amplify the difference between signals. It has ecellent stability, high versatility and immunity to noise. In a practical differential amplifier, the output depends not only upon the difference of the signals but also depends upon the common mode signal. Transistor Q and Q have matched characteristics. The values of R C and RC are equal. Re and Re are also equal and this differential amplifier is called emitter coupled differential amplifier. The output is taken between the two output terminals.

31 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM : COMMON MODE FORMULA: Common mode Gain (Ac) = VO / VIN Differential mode Gain (Ad) = V / VIN Where VIN = V V Common Mode Rejection Ratio (CMRR) = Ad/Ac Where, Ad is the differential mode gain Ac is the common mode gain.

32 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM : COMMON MODE OBSERVATION: For the differential mode operation the input is taken from two different sources and the common mode operation the applied signals are taken from the same source Common Mode Rejection Ratio (CMRR) is an important parameter of the differential amplifier. CMRR is defined as the ratio of the differential mode gain, Ad to the common mode gain, Ac. CMRR = Ad / Ac In ideal cases, the value of CMRR is very high.

33 EC6-Analog and Digital Circuits Lab PROCEDURE:. Connections are given as per the circuit diagram.. To determine the common mode gain, we set input signal with voltage Vin=V and determine Vo at the collector terminals. Calculate common mode gain, Ac=Vo/Vin.. To determine the differential mode gain, we set input signals with voltages V and V. Compute Vin=V-V and find Vo at the collector terminals. Calculate differential mode gain, Ad=Vo/Vin. 4. Calculate the CMRR=Ad/Ac. 5. Measure the dc collector current for the individual transistors. RESULT: Thus, the Differential amplifier was constructed and dc collector current for the individual transistors is determined. Differential gain Ad : Common mode gain Ac : CMRR : VIVA QUESTIONS. What is a differential amplifier?. What is common mode and differential mode inputs in a differential amplifier?. Define CMRR. 4. What is common mode signal? Write some applications of Differential amplifier.

34 EC6-Analog and Digital Circuits Lab EXP NO: 5.a DATE: CASCADE AMPLIFIER CIRCUIT AIM : To construct a cascade amplifier circuit and to plot the frequency response characteristics. APPARATUS REQUIRED: S.No. Name. Transistor. Resistor Capacitor Regulated power supply Signal Generator CRO Bread Board Connecting wires Range BC7.k,6k,6k,7 k,.k,k,6. k,k 47.μF (-)V (-)MHz MHz Quantity 5 Few THEORY: A cascade amplifier has many of the same benefits as a cascode. A cascade is basically a differential amplifier with one input grounded and the side with the real input has no load. It can also be seen as a common collector (emitter follower) followed by a common base. 5. By cascading a CE stage followed by an emitter-follower (CC) stage, a good voltage amplifier results. The CE input resistance is high and CC output resistance is low. The CC contributes no increase in voltage gain but provides a near voltage-source (low resistance) output so that the gain is nearly independent of load resistance. The high input resistance of the CE stage makes the input voltage nearly independent of input-source resistance. Multiple CE stages can be cascaded and CC stages inserted between them to reduce attenuation due to inter-stage loading. 4

35 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM: MODEL GRAPH: 5

36 EC6-Analog and Digital Circuits Lab TABULAR COLUMN : FREQUENCY RESPONSE OF CASCODE AMPLIFIER : Keep the input voltage constant (Vin) = Frequency Output Voltage Av=V/Vin (in Hz) Vo (in volts) Gain= log AV (in db) 6

37 EC6-Analog and Digital Circuits Lab PROCEDURE:. Connections are made as per the circuit diagram.. The waveforms at the input and output are observed for cascade operations by varying the input frequency.. The biasing resistances needed to locate the Q-point are determined. 4. Set the input voltage as V and by varying the frequency, note the output voltage. 5. Calculate gain= log (Vo / Vin.) 6. A graph is plotted between frequency and gain. RESULT: Thus, the Cascade amplifier was constructed and the gain was determined. VIVA QUESTIONS. What is meant by Cascading?. What is the overall gain of the two stage cascaded amplifier?. What methods are used for cascading? 4. What is the disadvantage of direct coupled cascade amplifier? 5. Write some application of cascaded amplifier. 7

38 EC6-Analog and Digital Circuits Lab EXP NO: 5.b DATE: CASCODE AMPLIFIER CIRCUIT AIM: To construct a cascode amplifier circuit and to plot the frequency response characteristics. APPARATUS REQUIRED: S.No... Name Transistor Resistor. Regulated power supply Signal Generator CRO Bread Board Capacitor Connecting Wires Range BC7 K,K,5 K,K,K. (-)V Quantity (-)MHz MHz Few.μF THEORY: A cascode amplifier consists of a common emitter amplifier stage in series with a common base amplifier stage. It it one approach to solve the low impedance problem of a common base circuit. Transistor Q and its associated components operate as a common emitter amplifier, while the circuit of Q functions as a common base output stage. The cascade amplifier gives the high input impedance of a common emitter amplifier, as well as the good voltage gain and frequency performance of a common base circuit. 8

39 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM: MODEL GRAPH : FREQUENCY RESPONSE OF CASCODE AMPLIFIER: 9

40 EC6-Analog and Digital Circuits Lab TABULAR COLUMN: Keep the input voltage constant (Vin) = Frequency (in Hz) Output Voltage Vo (in volts) Av=V/Vin Gain= log AV (in db) 4

41 EC6-Analog and Digital Circuits Lab PROCEDURE:. Connections are made as per the circuit diagram.. The waveforms at the input and output are observed for cascode operations by varying the input frequency.. The biasing resistances needed to locate the Q-point are determined. 4. Set the input voltage as V and by varying the frequency, note the output voltage. 5. Calculate gain= log (Vo / Vin.) 6. A graph is plotted between frequency and gain. RESULT: Thus, the Cascode amplifier was constructed and the gain was determined. VIVA QUESTIONS. What is meant by Cascoding?. What is the overall gain of the two stage cascaded amplifier?. What methods are used for cascading? 4. What is the disadvantage of direct coupled cascade amplifier? Compare cascade amplifier with cascade amplifier. 4

42 EC6-Analog and Digital Circuits Lab EXP NO: 6.a DATE: DETERMINATION OF BANDWIDTH OF SINGLE STAGE AMPLIFIERS AIM: To study the frequency response of a single stage RC coupled amplifier in a CE configuration, at low, middle, high frequency and demonstrate that gain bandwidth product is constant. APPARATUS REQUIRED: S.No. Name. Transistor NPN. Resistor Regulated power supply Function Generator CRO Bread Board Capacitor Range BC547.kΩ, kω,kω, Ω,variable resistance kω (-)V (-)MHz MHz Quantity μf,. μf, μf THEORY: The gain of an amplifier depends on frequency. As frequency decreases the gain starts to fall.the main cause of this is coupling capacitor Cc. Because it offers very high impedance at low frequency this causes decrease in output voltage. At high frequency the gain again falls because of the shunt capacitances made up of junction capacitances and wiring capacitances. The size of the coupling capacitor is so chosen that it offers negligible reactance to ac at operating frequencies. Ce acts as a by pass capacitor for ac signals.cb is that it must pass the input ac signal unattenuated. Hence the lower cut off frequency of the amplifier is determined by the coupling capacitors. The Coupling capacitor Cb along with resistance combination forms a high pass filter whose cut off frequency. 4

43 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM OF SINGLE STAGE RC COUPLED AMPLIFIER: 4

44 EC6-Analog and Digital Circuits Lab MODEL GRAPH: TABULATION: S.No. Frequency of input signal Output Voltage Gain () Gain () 44

45 EC6-Analog and Digital Circuits Lab 45

46 EC6-Analog and Digital Circuits Lab The lower cut off frequency at which gain the gain falls to 7.7% of its maimum value and the higher cut off frequency for which the gain falls to 7.7% of its maimum value. Bandwidth of an amplifier is given by BW = fh-fl PROCEDURE:. Make connection as shown in circuit diagram. After making sure that transistor is biased in active region feed the input signal from function generator (sine wave amplitude of mv) such that the output signal is undistorted.. Vary the input signal frequency from the function generator and observe for the voltage output (Vo) at the CRO, adjust the pot meter R4 to get the overall gain of. 4. Find the maimum voltage output by varying the frequency of input signal. Make sure that the amplitude of the input signal should remain same. 5. Record the voltage output in observation table by decreasing the frequency in small steps, below the frequency at which maimum voltage is obtained. Take the reading till voltage output is readable on the CRO. 6. In the similar manner, find the higher cut off frequency (fh) by increasing the frequency from the frequency where maimum gain is obtained. 7. Record the voltage output in observation table by increasing the frequency in small steps, above the frequency at which maimum voltage is obtained. Take the reading till voltage output is readable on the CRO. 9. Plot the frequency response curve as per the reading noted in the observation table.. Find out the lower cut-off frequency and higher cut-off frequency, where the gain falls up to 7.7% of maimum gain.. Calculate the bandwidth (f h f l).. Repeat the steps from step no. to, for the gain of by adjusting the R4 and make sure that amplitude of input signal should not change.. Find the gain bandwidth product and verify that this product is constant. RESULT: Thus the frequency response of a single stage RC coupled amplifier in a CE configuration, at low, middle, high frequency were studied Bandwidth of single stage amplifier is = 46

47 EC6-Analog and Digital Circuits Lab EXP NO: 6.b DATE: DETERMINATION OF BANDWIDTH OF MULTISTAGE AMPLIFIERS AIM: To study the frequency response of two stages RC coupled amplifier at low, middle, high frequency and demonstrate that the gain bandwidth product is constant. APPARATUS REQUIRED: S.No. Name. Transistor NPN. Resistor Regulated power supply Function Generator CRO Bread Board Capacitor Range BC547.kΩ, kω,kω, Ω,variable resistance kω (-)V (-)MHz MHz μf,. μf, μf Quantity THEORY: The gain of two stage amplifier depends on frequency.as frequency decreases the gain starts to fall.the main cause of this is coupling capacitor Cc. Because it offers very high impedance at low frequency this causes decrease in output voltage. At high frequency the gain again falls because of the shunt capacitances made up of junction capacitances and wiring capacitances. The Higher cut off frequency for which the gain falls to 7.7% of its maimum value is given by f h = fh (/n - )/ 47

48 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM OF TWO STAGE RC COUPLED AMPLIFIER: 48

49 EC6-Analog and Digital Circuits Lab MODEL GRAPH INPUT WAVE FORM : OUT PUT WAVE FORM OF STAGE : OUT PUT WAVE FORM OF STAGE : FREQUENCY RESPONSE : 49

50 EC6-Analog and Digital Circuits Lab BAND WIDTH: f - f = Hz The lower cut off frequency at which gain the gain falls to 7.7% of its maimum value is given by Bandwidth of two stage amplifier is given by: BW = f h - f L Gain BW = gain (fh-fl) Where fh is single stage higher cut off frequency fl is single stage lower cut off frequency n is no. of single stage in cascading f h is multistage higher cut off frequency f L is multistage lower cut off frequency 5

51 EC6-Analog and Digital Circuits Lab TABULATION: Output Voltage S.No Frequency Voltage Gain First-Stage Two-Stages First-Stage Two-Stages alone Coupled alone Coupled 5

52 EC6-Analog and Digital Circuits Lab PROCEDURE:. Make connection as shown in figure. After making sure that transistors are biased in active region feed the input signal from function generator (sine wave amplitude of mv) such that the output signal is undistorted.. Vary the input signal frequency from the function generator and observe for the voltage output (Vo) adjust the pot meter R4 to get the overall gain of. 4. To observe the frequency response of the first stage disconnects the second stage by removing the right lead of Cc, which is connected, to the base of second transistor. 5. Find the maimum voltage output by varying the frequency of input signal. 6. Record the voltage output in observation table by decreasing the frequency in small steps, below the frequency at which maimum voltage is obtained. Take the reading till voltage output is readable on the CRO. 7. In the similar manner, find the higher cut off frequency (fh) by increasing the frequency from the frequency where maimum gain is obtained. 8. Record the voltage output in observation table by increasing the frequency in small steps, above the frequency at which maimum voltage is obtained. Take the reading till voltage output is readable on the CRO. 9. Plot the frequency response curve as per the reading noted in the observation table.. Find out the lower cut-off frequency and higher cut-off frequency from the graph, where the gain falls up to 7.7% of maimum gain.. Calculate the bandwidth (f h f l).. Now to observe the effect of cascading, now before connecting the second stage with first stage, make sure that second stage of amplifier is identical and its gain as a single amplifier is same as stage first i.e. by adjusting the R4. 5

53 EC6-Analog and Digital Circuits Lab After making sure that transistors are biased in active region feed the input signal from function generator (sine wave amplitude of mv) such that the output signal is undistorted. 4 Find the maimum voltage output by varying the frequency of input signal. 5. Repeat the steps from step no.6 to. 6. Calculate the bandwidth of two stage amplifier as BW = f h - f L 7. Find the gain bandwidth product for both stages. Gain BW = gain (fh-fl) 8. Verify the gain and bandwidth product is constant RESULT: Thus the frequency response of a multi stage RC coupled amplifier in a CE configuration, at low, middle, high frequency were studied Bandwidth of two stage amplifier is = VIVA QUESTIONS. What is the necessity of cascading?. Define -db bandwidth.. Why RC-coupling is preferred in audio range. 4. Eplain various types of capacitors. 5

54 EC6-Analog and Digital Circuits Lab EXP NO: 7.a DATE: ANALYSIS OF COMMON EMITTER AMPLIFIE USING SPICE AIM: To design and construct a Common Emitter Amplifier using spice simulation tool. THEORY: The most common amplifier configuration for an NPN transistor is that of the Common Emitter Amplifier circuit. All types of transistor amplifiers operate using AC signal inputs which alternate between a positive value and a negative value so some way of presetting the amplifier circuit to operate between these two maimum or peak values is required. This is achieved using a process known as Biasing. Biasing is very important in amplifier design as it establishes the correct operating point of the transistor amplifier ready to receive signals, thereby reducing any distortion to the output signal. PROCEDURE:. Design the Circuit.. Number the nodes with values.. Add the following components in add meter such as oscilloscope, power supply and function generator. 4. Give the value for power supply, and input for function generator to receive the appropriate output. 5. Run and simulate the program. 54

55 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM: COMMON EMITTER AMPLIFIER: MODEL GRAPH: 55

56 EC6-Analog and Digital Circuits Lab PROGRAM: VIN SIN( M K) VCC 4 5 C. U C 5 7. U CE 6 U R 4 47K R K RC 4 5.6K RE 6 K RL 7 K Q 5 6 BC7 MODEL BC7NPN TRAN MS MS PROBE END RESULT: Thus Common Emitter Amplifier using spice was simulated. 56

57 EC6-Analog and Digital Circuits Lab EXP NO: 7.b DATE: ANALYSIS OF COMMON SOURSE AMPLIFIER USING SPICE AIM: To design and construct a Common Source Amplifier using spice simulation tool. THEORY: In electronics, a common-source amplifier is one of three basic single-stage fieldeffect transistor (FET) amplifier topologies, typically used as a voltage or transconductance amplifier. The easiest way to tell if a FET is common source, common drain, or common gate is to eamine where the signal enters and leaves. The remaining terminal is what is known as "common". In this eample, the signal enters the gate, and eits the drain. The only terminal remaining is the source. This is a common-source FET circuit. The analogous bipolar junction transistor circuit may be viewed as a transconductance amplifier or as a voltage amplifier. (See classification of amplifiers). As a transconductance amplifier, the input voltage is seen as modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of current flowing through the FET, changing the voltage across the output resistance according to Ohm's law. However, the FET device's output resistance typically is not high enough for a reasonable transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major drawback is the amplifier's limited high-frequency response. PROCEDURE:. Design the Circuit.. Number the nodes with values.. Add the following components in add meter such as oscilloscope, power supply and function generator. 4. Give the value for power supply, and input for function generator to receive the appropriate output. 5. Run and simulate the program. 57

58 EC6-Analog and Digital Circuits Lab CIRCUIT DIAGRAM: COMMON SOURCE WITH SELF BIAS: MODEL GRAPH: 58

59 EC6-Analog and Digital Circuits Lab PROGRAM: VS SIN( M 5KHZ) CG 4.7UF RG MEG RS 5.5K RD 4 4.7K VDD 5 5V CD 4 6 5UF CS 5 5UF RL 6 K JJI 4 5 BFW MODEL BFWNJF TRAN.MS.6MS PROBE END RESULT: Thus Common Source Amplifier using spice was simulated. 59

60 EC6-Analog and Digital Circuits Lab EXP NO: 8 DATE: DESIGN AND IMPLEMENTATION OF ADDER AND SUBRACTOR USING LOGIC GATES AIM: To design and construct a Half Adder, Full Adder, Half Subtractor and Full Subtractor circuits and verify their truth table using logic gates. APPARATUS REQUIRED: SL.NO COMPONENTS SPECIFICATION QUANTITY IC Trainer kit. EX-OR gate. IC 7486 NOT gate. IC 744 OR gate 4. IC 74 AND gate 5. IC748 Connecting 6. As Required Wires THEORY: Half Adder: A half-adder is a combinational circuit that can be used to add two binary bits. It has two inputs that represent the two bits to be added and two outputs, with one producing the SUM output and the other producing the CARRY. The Sum can be applied using EX-OR gate, carry output can be applied using an AND gate. Full Adder: A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of inputs and outputs. Two of the input variables, represent the significant bits to be added. The third input represents the carry from previous lower significant position. The logic diagram of the full adder can also be implemented with two half-adders and one OR gate. The S output from the second half adder is the eclusive-or of Cin and the output of the first half-adder 6

61 EC6-Analog and Digital Circuits Lab HALF ADDER: TRUTH TABLE: Inputs A B K- MAP SIMPLIFICATION: Outputs Carry Sum (C) (S) LOGIC DIAGRAM: FULL ADDER: K-Map Simplification: TRUTH TABLE: Inputs Outputs A B Cin Logic Diagram: Full Adder: Sum (S) Carry (C out) Full Adder using Two Half Adders: 6

62 EC6-Analog and Digital Circuits Lab 6

63 EC6-Analog and Digital Circuits Lab Half Subtractor: A half-subtractor is a combinational circuit that can be used to subtract one binary digit from another to produce a DIFFERENCE output and a BORROW output. The BORROW output here specifies whether a has been borrowed to perform the subtraction. The difference can be applied using EX-OR gate, borrow output can be applied using an AND gate and an inverter. Full Subtractor: A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and also takes into consideration whether a has already been borrowed by the previous adjacent lower minuend bit or not. As a result, there are three bits to be handled at the input of a full subtractor, namely the two bits to be subtracted and a borrow bit designated as B in. There are two outputs, namely the DIFFERENCE output D and the BORROW output B o. The BORROW output bit tells whether the minuend bit needs to borrow a from the net possible higher minuend bit PROCEDURE:. Connections are given as per the logic diagram.. Logic inputs are given as per the truth table.. Observe the logic output and verify with their truth tables. RESULT: Thus half adder, full adder, half subtractor and full subtractor circuits was designed using logic gates and their truth tables were verified. VIVA QUESTIONS. What is truth table and boolean epression?. What is combinational circuit?. Implement half adder and Full adder with NAND Gate only? 6

64 EC6-Analog and Digital Circuits Lab EXP NO: 9 DATE: DESIGN AND IMPLEMENTATION OF CODE CONVERTER AIM: To design and implement 4-bit. Binary to Gray code Converter. Gray to Binary code Converter. BCD to Ecess- code Converter 4. Ecess- code to BCD Converter APPARATUS REQUIRED: SL.NO COMPONENTS. IC Trainer kit. EX-OR gate. NOT gate 4. OR gate 5. -Input AND gate 6. -Input AND gate 7. Connecting Wires SPECIFICATION QUANTITY IC7486 IC744 IC74 IC748 IC74 As Required THEORY: An availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The input variable are designed as B,B,B,B and the output variables are designed as G,G,G,G. From the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable. To convert from binary code to Ecess- code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean epressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. 64

65 EC6-Analog and Digital Circuits Lab BINARY TO GRAY CODE CONVERTER: TRUTH TABLE: Binary code Gray code B B B B G G G K- Map Simplification: G Logic Diagram: 65

66 EC6-Analog and Digital Circuits Lab GRAY TO BINARY CODE CONVERTER: TRUTH TABLE: Gray code K-Map Simplification: Binary code G G G G B B B B Logic Diagram: 66

67 EC6-Analog and Digital Circuits Lab BCD TO EXCESS- CODE: Truth table: BCD code K-Map Simplification: Ecess- code B B B B E E E E Logic Diagram: 67

68 EC6-Analog and Digital Circuits Lab EXCESS- TO BCD CONVERTER: Truth Table: Ecess- code K-Map Simplification: BCD code E E E E B B B B Logic diagram: 68

69 EC6-Analog and Digital Circuits Lab PROCEDURE:. Connections are given as per the logic diagram.. Logic inputs are given as per the truth table.. Observe the logic output and verify with the truth tables. RESULT: Thus the 4-bit. Binary to Gray code Converter. Gray to Binary code Converter. BCD to Ecess- code Converter 4. Ecess- code to BCD Converter was designed and implemented. VIVA QUESTIONS. What are the gray codes?. What are the properties of Gray codes?. What is the advantages and application of Gray codes? 4. Convert into binary code? 5. Convert into Gray Code? 69

70 EC6-Analog and Digital Circuits Lab EXP NO: DATE: DESIGN OF 4-BIT ADDER / SUBTRACTOR AND BCD ADDER AIM: To Design and implement the 4-bit adder/ subtractor and BCD adder using IC 748. APPARATUS REQUIRED: SL.NO COMPONENT SPECIFICATION QUANTITY -. IC Trainer kit. 4-bit binary full adder IC 748. EX-OR gate IC AND gate IC OR gate IC Connecting Wires - As Required THEORY: 4-Bit binary adder/ subtractor: The 4-bit binary adder/ subtractor circuit performs the operation of both addition and subtraction. It has two 4-bit inputs A, A, A, A and B, B, B, B. The mode input M controls the operation of the circuit. When M=, the circuit is an adder and when M=, the circuit becomes a Subtractor. Each eclusive-or gate receives input M and one of the inputs of B. When M=, the operation is B = B. The full adders receive the value of B and the input carry is, and the circuit performs the addition operation, A+ B. When M=, the operation is B = B and C=. The B inputs are all complemented and a is added through the input carry. Thus the circuit performs the subtraction operation, i.e., A+ ( s complement of B) = A- B. 7

71 EC6-Analog and Digital Circuits Lab PIN DIAGRAM FOR IC 748: LOGIC DIAGRAM: 4- BIT BINARY ADDER: 7

72 EC6-Analog and Digital Circuits Lab 4- BIT BINARY SUBTRACTOR: 4 BIT BINARY ADDER/SUBTRACTOR: 7

73 EC6-Analog and Digital Circuits Lab TRUTH TABLE: Input data A Input data B Addition Subtraction A A A A B B B B C S S S S B D D D D LOGIC DIAGRAM: BCD ADDER: 7

74 EC6-Analog and Digital Circuits Lab TRUTH TABLE: 74

75 EC6-Analog and Digital Circuits Lab 4- Bit BCD Adder: The digital system handles the decimal number in the form of binary coded decimal numbers (BCD). A BCD adder is a circuit that adds two BCD bits and produces a sum digit also in BCD.In eamining the contents of the table, it is apparent that when the binary sum is equal to or less than (), the corresponding BCD number is identical, and therefore no conversion is needed. When the binary sum is greater than 9 (), we obtain a non-valid BCD representation. The addition of binary 6 () to the binary sum converts it to the correct BCD representation and also produces an output carry as required.the logic circuit to detect sum greater than 9 can be determined by simplifying the Boolean epression of the given truth table. The two decimal digits, together with the input carry, are first added in the top 4-bit binary adder to provide the binary sum. When the output carry is equal to zero, nothing is added to the binary sum. When it is equal to one, binary () is added to the binary sum through the bottom 4-bit adder. The output carry generated from the bottom adder can be ignored, since it supplies information already available at the output carry terminal. The output carry from one stage must be connected to the input carry of the net higher-order stage. PROCEDURE:. Connections are given as per the logic diagram.. Logic inputs are given as per the truth table.. Observe the logic output and verify with the truth tables. RESULT: Thus the 4-bit adder/ subtractor and BCD adder using IC 748 was designed and implemented. VIVA QUESTIONS :. What is mean by BCD addition?. Perform BCD addition of + 6. Why we need to add 6 in BCD addition? 4. BCD Means and range? 75

76 EC6-Analog and Digital Circuits Lab EXP NO: DATE: DESIGN AND IMPLEMENTATION OF MULTIPLEXER DEMULTIPLEXER AIM: To design and implement multipleer and demultipleer using logic gates. APPARATUS REQUIRED: SL.NO COMPONENT. IC Trainer kit. -I/P AND GATE. NOT GATE SPECIFICATION - QUANTITY IC74 IC744 IC74 4. OR GATE 5. Connecting Wires As Required THEORY Multipleer: Multipleer means transmitting a large number of information units over a small number of channels or lines. A digital multipleer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are n input line and n selection lines whose bit combination determine which input is selected. It is called as data selector, because the output depends on the input data bit that is selected. Demultipleer: The function of Demultipleer is in contrast to multipleer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultipleer is also known as a data distributor. Decoder can also be used as Demultipleer.In the :4 demultipleer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line. 76

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