MSTM-SEC1 Simplified Control Timing Module

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1 MSTM-SEC1 Simplified Control Timing Module 2111 Comprehensive Drive Aurora, Illinois Phone: Fax: US Headquarters: European Headquarters: General Description The Connor-Winfield Stratum SEC1 (SDH Equipment Slave Clock - Option 1) Control Timing Module acts as a complete system clock module for SDH Slave Clock timing applications. The MSTM is designed for external control functions. Full external control input allows for selection and monitoring of any of four possible operating states: 1) Holdover; 2) External Reference #1; 3) External Reference #2; and 4) Free Run. Table 1 illustrates the control signal inputs and corresponding operational states. In the absence of External Control Inputs (A,B), the MSTM enters the Free Run mode and signals an External Alarm. The MSTM will enter other operating modes upon application of a proper control signal. Mode 1 operation (A=1, B=0) results in an output signal that is phase locked to the External Reference Input #1. Mode 2 operation (A=1, B=1) results in an output signal at or near the frequency as determined by the latest (last) lockedsignal input values and the holdover performance of the MSTM. Free Run ModeFree Run mode operation (A=0, B=0) is a guaranteed output of 4.6 ppm of the nominal frequency. Alarm signals are generated at the Alarm Output during Holdover and Free Run operation. Alarm Signals are also generated by loss-of-lock, loss of Reference, and a Tune-Limit indication from the PLL. A Tune- Limit alarm signal indicates that the VCXO tuning voltage is approaching within % the limits of its lock capability and that the External Reference Input may be erroneous. A high level indicates an alarm condition. Real time indication of the operational mode is available at unique operating mode outputs on pins 1-4. Control loop filters effectively attenuate any reference jitter and smooth out phase transients.

2 Table 1 Absolute Maximum Rating Symbol Parameter Minimum Nominal Maximum Units Notes V CC Power Supply Voltage (Vcc to Gnd) Volts 1.0 V IN Input Voltage with respect to ground Vcc+0.5 Volts 1.0 T STG Storage Temperature C 1.0 Table 2 Input and Output Characteristics Symbol Parameter Minimum Nominal Maximum Units Notes V IH High level input voltage (TTL Compatible) Vcc V V IL Low level input voltage (TTL Compatible) V T IN Input signal transition time ns C IN Input capacitance pf C OUT Output capacitance pf V High level output OH I OH = -8.0 ma, Vcc minimum V V OL High level output I OL = -8.0 ma, Vcc minimum V T HL Clock out transition time high-to-low, no load ns T LH Clock out transition time low-to-high, no load ns T Input 8 khz reference signal positive RP pulse width ns T Input 8 khz reference signal negative RN pulse width ns T OP Standard Operating Temperature 0-70 C Operating Specifications Table 3 Parameter Specifications Frequency Range MHz, MHz 2.0 Power Supply voltage 5 V DC (±5%) Supply Current 60 ma Typical at MHz Timing Reference Inputs 8 khz Jitter and Phase Tolerance ITU-T G Wander Generation ITU-T G Free Run Accuracy ±4.6 ppm Holdover Stability ±0.37 ppm 3.0 Initial Offset 0.05 ppm Temperature 2.0 ppm Drift 0.01 ppm/day Holdover History 40 seconds Pull-in / Hold-in Range ±4.6 ppm Minimum 4.0 Lock Time TBD TVL Alarm 1 = WARNING: Reference nearing operational limit 5.0 Preliminary Data Sheet #: TM029 Page 2 of 16 Rev: P02 Date: 09/07/01

3 Table 4 Control Inputs & Operational States Control Input Operational Mode REF 1 REF 2 Holdover Free Run PLL_TVL Alarm A B Output 0 0 Free Run (Default) External Normal Reference Tune Limit #1 LOR + LOL External Normal Reference Tune Limit #2 LOR + LOL Holdover NOTES: 1.0 Operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2.0 Consult factory for other output frequencies. 3.0 Holdover stability is the cumulative fractional frequency offset containing Initial Offset, Temperature, and Drift components as described by ITU-T G Pull-in range is the minimum frequency deviation on the reference inputs to the timing module that can be overcome to pull itself into synchronization with the reference. 5.0 A 1 level indicates unit is within the extreme % of its operating range tracking the reference (~11ppm). Consult factory for use as a reference qualifier. Pin Assignment Figure 1 Block Diagram Figure 2 PLL TVL EX REF 1 EX REF 2 2:1 MUX Phase Comparator Lock and Detection Free Run Hold Over Alarm Out Sync Out CNTL A CNTL B 2:4 MUX Free Run Ref #1 Ref #2 Hold Over DAC Filters DAC SEC VCTCXO Tuning Voltage FIFO Monitor PLL TVL Preliminary Data Sheet #: TM029 Page 3 of 16 Rev: P02 Date: 09/07/01

4 Pin Description Table 5 Pin # Pin Name Pin Information 1 Holdover Output. High when the control inputs select Holdover 2 REF 1 Output. High when the control inputs select EX REF 1 3 REF2 Output. High when the control inputs select EX REF2 4 Free Run Output. High when the control inputs selects Free Run 5 Gnd Ground 6 Alarm_Out Output. =1,If (Free Run + Holdover + LOR + LOL + PLL_TVL) 7 Control A Mode control input 8 Control B Mode control input 9 PLL_TVL Tuning Voltage Alarm. =1 If Capture Range Near % of Extreme (~11ppm) Gnd Ground 11 SYNC_OUT Synchronized output 12 Gnd Ground 13 N/C No connection 14 Gnd Ground 15 Ex REF 2 External Reference #2 Input (8 khz) 16 Gnd Ground 17 Ex REF 1 Input. External Reference #1 Input (8 khz) Vdc +5 Volt DC supply Preliminary Data Sheet #: TM029 Page 4 of 16 Rev: P02 Date: 09/07/01

5 1.0E-6 0.0E-9.0E-9 1.0E-9 1.0E-6 0.0E-9.0E-9 1.0E-9 TDEV GR1244-Fig5.1 GR1244-Fig5-3 S a m p le M T IE D a ta fo r S T M -S 3 /M S T M -S 3 S am ple W an de r G e n e ratio n (T D E V ) for S T M /M S T M -S 3 T ypical response seco nd test - Jitter applied (2 H z) ref date A P R kdh Typical response seco nd test - Jitter applied (2 H z) ref date A P R kdh 0.0E-3 1.0E+0.0E+0 0.0E+0 1.0E+3.0E+3 Observation Tim e (s) 0.0E-12.0E-3 0.0E-3 1.0E+0.0E+0 0.0E+0 1.0E+3 C opyright 1998 C o nno r-w infield alll rights reserved I n te g r a t io n T im e ( s e c ) MTIE M a s k (A ) M a s k (B ) M a s k G R C o p yrig h t C o n n o r-w in fie ld a ll righ ts re s e rve d Typical Application Figure 3 g BITS System Signal Input Select Timing Card #1 Line Card 1 A S A B MUX Y CW s STM/MSTM module B MUX Y CW s SCG 2000/4000 Clock out S RCV Timing Card #2 Line Card N S A B Y MUX CW s STM/MSTM module A B MUX Y CW s SCG 2000/4000 Clock out S RCV System Select Typical System Test Set-up Figure 4 This device supplies system time information. It can be thought of as supplying "absolute time" reference inform ation GPS or LORAN Timing Source Possible Choices Include Stanford Research Model: FS700 Truetime Model XXX MHz MTIE (s Target System Under Test External Reference Input MHz External Reference Input Arbitrary W aveform Generator Arbitrary W aveform Generator [Noise Source] DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 khz clock RZ with noise modulation Noise Modulation Input Clock or BITS logic level clock input (TTL, CMOS, etc.) Timing Card Line Card Timing Card OC-3 Line Card OC-12 Line Card OC-48 Line Card DS-1 Line Card TDEV (se c Standards Compliance Documents MTIE, TDEV, W ander Transfer, and W ander Generation Plots D S1 rate [1.544 M Hz] BITS Bipolar MHz Time-stamped ensemble based on absolute time reference (MHz input) MHz Tektronix SJ300E DS-1, OC-3, OC-12 electrical or optical signals External Reference Input HP533A Modulation Analyzer / Time Interval Analyzer Phase Error data output External Reference Input TEKTRONIX SJ300E W ander Analyzer data (IEEE-488) IEEE-488 Controller Platform for software HP 53305A Phase Analyzer HP E1748A Sync Measurement Tektronix W ander Analyzer Preliminary Data Sheet #: TM029 Page 5 of 16 Rev: P02 Date: 09/07/01

6 Typical Calibrated Wander Transfer TDEV Figure TDEV (ns) 0 TDEV (ns) GR1244, Fig Typical Wander Generation MTIE Figure Integration Time (Sec.) MTIE (ns) GR1244, Fig 5.2 (A) GR1244, Fig 5.2 (B) GR , Fig 5.17 M T IE (n s ) O bservation Tim e (sec.) Preliminary Data Sheet #: TM029 Page 6 of 16 Rev: P02 Date: 09/07/01

7 Typical Wander Generation TDEV Figure 7 0 TDEV (ns) GR1244, Fig TDEV (ns) In te g ra tio n T im e (s ec.) 1µs Phase Transient TIE Figure TIE (ns) Time (sec) Preliminary Data Sheet #: TM029 Page 7 of 16 Rev: P02 Date: 09/07/01

8 Typical Phase Transient MTIE Figure MTIE (ns) 0 GR-253, Fig M TIE (ns) Observation Time (sec) Entry Into Hold Over Figure MTIE (ns) 0 GR-1244 Objective, Fig. 5-8 GR-1244 Requirement, Fig. 5-8 Typical M TIE Observation Time (seconds) Preliminary Data Sheet #: TM029 Page 8 of 16 Rev: P02 Date: 09/07/01

9 Return from Hold Over Figure MTIE (ns) 0 GR-1244 Requirement, Fig. 5-7 MTIE (ns) Typical M TIE Observation Time (sec.) Preliminary Data Sheet #: TM029 Page 9 of 16 Rev: P02 Date: 09/07/01

10 MSTM-S3-TR Mode Indicator Delay Figure 12 Change in Operational Mode Operational Mode Indicator t m 2 msec < t m < msec Tuning Voltage Limit Alarm Timing Diagram Figure 13 TVL Limit High Frequency Sync_Out (Nominal Frequency) TVL Limit Low Frequency TVL Alarm & Alarm Out t 0 < t < msec *The DAC is updated only when the output changes level. The maximum update rate is 8 khz Preliminary Data Sheet #: TM029 Page of 16 Rev: P02 Date: 09/07/01

11 Loss of Reference Timing Diagram Figure 14 External Reference Input Alarm ton A toff A 2 msec < taon < msec 0 msec < t off < msec A Solder Clearance Figure " MAX..020".030" PIN LAND ALL SOLDER AND/OR WIRE TAGS SHALL NOT EXTEND MORE THAN.020" BELOW PC BOARD BOTTOM SURFACE Preliminary Data Sheet #: TM029 Page 11 of 16 Rev: P02 Date: 09/07/01

12 MECHANICAL OUTLINE: The mechanical outline of the MSTM-S3-TR is shown in Figure 17. The board space required is 2 x 2. The pins are.040 in diameter and are.150 in length. The unit is spaced off the PCB by.030 shoulders on the pins. Due to the height of the device it is recommended to have heat sensitive devices away where the air flow might not be blocked. PAD ARRAY AND PAD SPACING: The pins are arranged in a dual-in-line configuration as shown in Figure 16. There is.2 space between the pins in-line and each line is separated by 1.6. See Figures 17 & 18 and Table 6. PAD CONSTRUCTION: The recommended pad construction is shown in Figure 18. For the pin diameter of.040 a hole diameter of.055 is suggested for ease of insertion and rework. A pad diameter of.150 is also suggested for support. This leaves a spacing of.050 between the pads which is sufficient for most signal lines to pass through. SOLDER MASK: A solder mask is recommended to cover most the top pad to avoid excessive solder underneath the shoulder of the pin to avoid rework damage. See Table 6 and Figure 19. VIA KEEP OUT AREA: It is recommended that there be no vias or feed throughs underneath the main body of the module between the pins. It is suggested that the traces in this area be kept to a minimum and protected by a layer of solder mask. See Figure 18. GROUND AND POWER SUPPLY LINES: Power specifications will vary depending primarily on the temperature range. At wider temperature ranges starting at 0 to 70 deg. C., an ovenized oscillator, OCXO, will be incorporated. The turn-on current for an OCXO requires a peak current of about.4a for about a minute. The steady state current will the vary from ma depending on the temperature. It is suggested to plan for the peak current in the power and ground traces pin 18 and pin 5. The other four ground pins, 12, 14, and 16 are intended for signal grounds. POWER SUPPLY REGULATION: Good power supply regulation is recommended for the MSTM-S3-TR The internal oscillators are regulated to operate from volts. Large jumps within this range may still produce varying degrees of wander. If the host system is subject to large voltage jumps due to hot-swapping and the like, it is suggested that there be some form of external regulation such as a DC/DC converter. SOLDERING RECOMMENDATIONS: Due to the sensitive nature of this part, hand soldering or wave soldering of the pins is recommended after reflow processes. WASHING RECOMMENDATIONS: The MSTM-S3-TR is not in a hermetic enclosure. It is recommended that the leads be hand cleaned after soldering. Do not completely immerse the module. MODULE BAKEOUT: Do not bakeout the MSTM-S3-TR Preliminary Data Sheet #: TM029 Page 12 of 16 Rev: P02 Date: 09/07/01

13 Package Dimensions Figure 17 Characteristic Measurements Table [40.64 mm] [5.08 mm] Characteristic Item Measurement (inches) [50.80 mm] [5.08 mm] Pad to Pad Spacing Solder pad top O.D [5.08 mm] [14. mm] Solder pad top I.D [50.80 mm] Solder pad bottom O.D Solder pad bottom I.D [14.86 mm] Maximum Height Solder mask top dia [5.08 mm] [1.14 mm] Solder mask bottom dia [1.98 mm] [1.02 mm] Pin row to row spacing [3.05 mm] Recommended Footprint Dimensions Figure 18 Side Assembly View Figure Pin #1 Pin # I.D. Ø0.055 Finished Hole TOP SIDE SOLDER RESIST (OVER PAD) PCB O.D. Ø0.150 Copper Pad Via Keepout Area BOTTOM SIDE SOLDER RESIST (UP TO PAD) SIDE VIEW Preliminary Data Sheet #: TM029 Page 13 of 16 Rev: P02 Date: 09/07/01

14 Preliminary Data Sheet #: TM029 Page 14 of 16 Rev: P02 Date: 09/07/01

15 Revision Revision Date Note P00 7/27/01 Preliminary Release P01 8/01/01 Added POR figure and Tri-state pin P02 9/07/01 Added power supply voltage to Table 3 Preliminary Data Sheet #: TM029 Page 15 of 16 Rev: P02 Date: 09/07/01

16 2111 Comprehensive Drive Aurora, Illinois Phone: Fax:

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