THE present trends in the development of integrated circuits
|
|
- Quentin Hill
- 5 years ago
- Views:
Transcription
1 On-chip Prmetric Test of -2 Ldder Digitl-to-Anlog Converter nd Its Efficiency Dniel Arbet, Vier Stopjková, Jurj Brenkuš, nd Gábor Gyepes Abstrct This pper dels with the investigtion of the fult detection in seprted prts of mixed-signl integrted circuit exmple by implementing prmetric test methods. The experimentl Circuit Under Test (CUT) consisting of n 8-bit binryweighted -2 ldder digitl-to-nlog converter nd dditionl on-chip test hrdwre ws designed in stndrd 0.35μm CMOS technology. For detection of ctstrophic nd prmetric fults considered in different prts of the CUT, two dedicted prmetric test methods: oscilltion-bsed test technique nd I DDQ monitoring were used. For the opertionl mplifier, onchip nd off-chip pproches hve been used to compre the efficiency of both pproches in covering ctstrophic fults tht re hrd to detect. For respective converter prts, the excelent fult coverge of 94.21% of hrd-detectble fults by the proposed prmetric tests ws chieved. Index Terms Fult detection, ctstrophic fults, prmetric fults, on-chip prmetric test, mixed-signl test I. INTODUCTION THE present trends in the development of integrted circuits nd new dvnced technologies enble integrtion of complex digitl nd mixed-signl systems on single chip. These complex systems, know s Systems-on-Chip (SoC), cn include digitl, nlog, nd F circuits s well s MEMS structures, microsensors nd nother different cores. No doubt, testbility of the respective prts in such systems is gretly decresed [1]. Stndrd test methods cnnot be strightforwrdly used to test complex mixed-signl systems. Therefore, severl utomtic test equipments (ATE), ech dedicted to prticulr core integrted in the system, would be needed. Such pproch increses costs of IC production uncceptbly, since it requires the expensive nd dvnced ATE. Due to this reson, test methodology for complex systems becomes the upmost importnt. Test engineers hve been looking for new test methods nd pproches, which cn ssure better testbility, higher fult coverge nd high qulity of integrted system production. Prmetric test methods re most commonly used for testing nlog nd mixed-signl integrted circuits (IC). These methods re bsed on the monitoring of specific circuit s prmeter such s voltge, supply current, frequency, etc. Evlution of the specific prmeter in complex system is This work ws supported in prt by the Ministry of Eduction, Science, eserch nd Sport of the Slovk epublic under grnts VEGA 1/0285/09, VEGA 1/1008/12, VMSP-II APVV nd the Centre of Excellence for Smrt Technology, Systems nd Services II, ITMS Code All uthors re with Institute of Electronics nd Photonics, Fculty of Electricl Engineering nd Informtion Technology, Slovk University of Technology, Ilkovicov 3, Brtislv , Slovki (corresponding uthor: D. Arbet, phone: ; fx: ; e-mil: dniel.rbet@stub.sk). difficult becuse it requires sophisticted sensing nd nlyses of the selected prmeter in terms of dditionl hrdwre needed, setting the Pss/Fil limit, robustness, etc. (in comprison to the simple logic test). On the other hnd, prmetric test, performed for prt of the complex system, my be the only proper nd/or implementble test pproch in some pplictions [2]. Such pproch is bsed on dividing the complex system into smller prts tht could be esily tested seprtely, ech prt by dedicted test method. In this pper, n 8-bit -2 ldder digitl-to-nlog converter (DAC) ws used s the test vehicle. Considering the structure of this circuit, it ws split into two prts, which hve been tested seprtely using two different prmetric test methods. Thus, the control logic, used for selecting the test method nd switching the circuit mode (test/functionl), hs been designed. In Section 2, the preliminry work done in the respective re is described. Experimentl CUT is presented in more detils in Section 3. In Section 4, the proposed test strtegies employed in test of the respective prt of the DAC re described. In Section 5, influence of dditionl test hrdwre on the DAC preformnce is ddressed. Simultion results nd chieved fult coverge re summrized in Section 6. In the lst section, the efficiency of the proposed test method through the obtined experimentl results is discussed. II. PELIMINA WOK Digitl-to-nlog converters nd nlog-to-digitl converters (ADC) re very often used circuits in the mixed-signl integrted systems. However, to test such systems by conventionl externl pproches, ccurte mesurement instruments s well s dvnced nd costly ATE [3] re necessry. Therefore, Built-In Self Test (BIST) pproches represent the best solution or sometimes, even the only possible wy of testing mixed-signl circuits like converters re. Thus, BIST cn significntly reduce test time nd overll cost since the most difficult tsks re performed directly on chip. In the lst yers, mny BIST structures hve been published, nd severl different modifictions of BIST pproch pplicble to DAC nd ADC hve been proposed [4] [6]. The IEEE stndrd for terminology nd test methods of digitlto-nlog converters is described in [7]. In [8] [10], different on-chip test hrdwre hs been proposed nd used for testing the dt converters. BIST metodologies using different onchip input stimuli genertors were described in [11] nd [12]. A BIST scheme for DAC testing, bsed on the undersmpling technique presented in [13], ws proposed in [14]. The oscilltion-bsed test for nlog-to-digitl nd digitl-tonlog converters hs been ddressed in [6], [15] nd [16].
2 OUTPUT Another BIST structures for very populr -2 ldder DAC were ddressed in [9], [17]. However, the efficiency of the existing on-chip test pproches in covering rel hrd-detctble fults hs still some limittions, nd it shoud be improved in order to ssure the necessry relibility. Moreover, most of the prmetric test methods re not mture enough to be implemented s fully on-chip test pproch, since they suffer either from complexity of the hrdwre or from test stimuli gerertion. In this pper, on-chip prmetric test of 8-bit -2 ldder DAC is presented. The converter is split into two prts: the opertionl mplifier nd -2 resistor network, which re tested seprtely by oscilltion test method [18] [21] nd I DDQ monitoring [22] [25], respectively. This pproch is esy to implement nd offers rther high fult coverge of hrd-detectble fults. Furthermore, input test stimuli re esy to generte on-chip, nd the proposed pproch is ble to identify defective prt of the CUT. III. EXPEIMENTAL CICUIT UNDE TEST Fig. 1 shows the block digrm of the experimentl mixedsignl circuit designed in 0.35μm CMOS technology, which consists of the selected converter nd the necessry on-chip test hrdwre, including the control logic used for switching the circuit into the test mode. As mixed-signl CUT, n 8- bit binry-weighted -2 ldder DAC hve been designed nd used in our experiment. In the test mode, the DAC circuit is split into two seprted prts: 2-stge opertionl mplifier (OPAMP) nd the -2 resistor network. Using two dditionl inputs TEST nd MODE, the circuit cn be switched in one of two test modes in order to test the respective prt of the converter seprtely, ech by employing dedicted prmetric test method. Fig. 1. CL LOAD / MODE TEST VEF Additionl test hrdwre nd control logic -2 resistor network VDD Dt inputs GND 2-stge opertionl mplifier D7 D6 D5 D4 D3 D2 D1 D0 Block digrm of the mixed-signl CUT used IV. POPOSED TEST STATEG A. Off-chip test of opertionl mplifier For the fult detection in the opertionl mplifier (OPAMP), the oscilltion test method trnsforming the mplifier into n oscilltor by inserting feedbck C network ws used. Using this method, different fults present in the mplifier nd cusing devition either in the oscilltion frequency or OUTPUT I EF1 I EF2 2 D0 D1 OPAMP F C buffer 1 On-chip OPAMP Fig. 2. Circuit digrm of the OPAMP circuit trnsformed into n oscilltor (without control logic) in the mplitude of oscilltions (exceeding the nominl fultfree tolernce rnge) cn be detected [20]. Components in the feedbck network were connected externlly (by T-gtes) using two dditionl input pins (DO nd D1) nd the output pin OUTPUT (Fig. 2). In this configurtion, smller devition in the oscilltion frequency nd the mplitude of oscilltions were reched. The feedbck resistor F, which is prt of the DAC, is clmped to ground using two MOS trnsistors. A buffer is defult prt of the converter but in this topology, it ws lso used to seprte the OPAMP from possible externl influences. The OPAMP cn be tested by pplying logic 1 nd logic 0 to pins TEST nd MODE, respectively (Fig. 1). Then the common control logic (not depicted in Fig. 2) genertes the control signls () for T- gtes tht for test purposes, disconnect the OPAMP from the -2 resistor network nd connect the feedbck network. T-gtes were used for insertion of the feedbck. However, they my cuse the CUT performnce degrdtion nd therefore, their ON- nd OFF- resistnces must be s low s possible nd s high s possible, respectively. Hence, the ON-resistnce of T-gtes, which re ppering in the signl pth, must be minimized to prevent the undesired performnce degrdtion [26]. The fult-free tolernce bnds (representing process vritions nd temperture influence) for the oscilltion frequency nd the mplitude of the oscilltion frequency were obtined by Monte Crlo nlysis, nd re depicted in Fig. 3 nd Fig. 4, respectively. Devitions (obtined by 50 runs) of ±13% in the oscilltion frequency nd of ±2.85% in the oscilltion mplitude were observed. B. On-chip test of opertionl mplifier Previously, the feedbck network nd pssive components were relized externlly using discrete devices in order to chieve higher ccurcy nd smller devition in the oscilltion
3 Number of bins mu = M sd = K N = 50 devition = +/- 13% IN NON_INV IN INV TEST C OPAMP OUT TEST TEST f OSC k 950.0k 1.0M 1.1M 1.1M 1.1M frequency 2 F Fig. 3. Nominl devition in the oscilltion frequency Fig. 5. Circuit digrm of the OPAMP circuit trnsformed into n oscilltor (without control logic) Number of bins mu = sd = m N = 50 devition = +/- 2.35% obtined for externl reference oscilltor (Fig. 6). 35 Off-chip FB with externl oscilltor 30 On-chip FB with Schmitt oscilltor mplitude Frequency Fig. 4. Fult-free devition in the mplitude of oscilltions 10 5 frequency nd the mplitude of oscilltions. Tking into ccount SoC testing requirements, where sort of BIST strtegy to test the mixed-signl cores (e.g. DACs) is demnded, n on-chip test should be performed. Therefore, in such cse, the OPAMP feedbck network must be connected internlly, using devices with bout 20% devition in technology prmeters. In [21], such OBIST strtegy for testing OPAMP s prt of complex nlog nd mixed-signl systems is described. To evlute the efficiency of this test strtegy, the circuit oscilltion frequency is then compred to the reference frequency given by Schmitt trigger oscilltor, which ws used s the onchip frequence reference to compenste technology vritions. Fig. 5 shows the circuit digrm of the on-chip oscilltor using n on-chip feedbck network for trnsforming the OPAMP into the oscilltor. The oscilltion frequency ws evluted by countering number of oscilltion pulses exhibited by the CUT during time intervl generted by the reference oscilltor. Influence of technology vritions on the oscilltion frequency for fultfree CUT ws obtined from Monte Crlo nlysis. MC nlysis of technology vritions of ±3σ ws performed for ll devices used in the CUT nd dditionl test hrdwre. To demonstrte the efficiency of the on-chip oscilltion test pproch, the fult-free tolernce bnds obtined for the onchip feedbck network reliztion ws compred to the one f mes / f nom Fig. 6. Comprison of the oscilltion frequency tolernce bnds for on-chip nd off-chip reference oscilltor solutions From Fig. 6, one cn observe tht devition in the oscilltion frequency for the on-chip feedbck network nd the on-chip reference oscilltor is pretty much the sme s the oscilltion frequency devition obtined by off-chip feedbck network nd the externl oscilltor. This result proves tht the oscilltion test strtegy offers the on-chip test of the opertionl mplifier s seprted prt of the experimentl DAC. With the on-chip test, stndrd mixed-signl SoC test requirements could be fulfilled. A more detiled description of the proposed on-chip test strtegy, including the oscilltion frequency evlution nd the PASS/FAIL threshold selection, is presented in [21]. C. Test of -2 resistor network The -2 ldder is resistor network tht uses cscded structure of current dividers, which generte binry-weighted currents in the respective brnches, s shown in Fig. 7. In idel
4 V EF S8 S8 I 8 I 7 I 1 I 0 S8 S7 S7 S1 S1 S8 S7 S7 S1 S1 I EF1 This procedure goes on till the lst two current brnches re processed. The current difference t ech step of the proposed test procedure cn be expressed s follows: ( N ) I diff N = I N I N 1 i=0 (1) Fig. 7. V VSS_EF Circuit digrm of the -2 ldder I EF2 cse, the dividing rtio should be 2:1 but becuse of resistors mismtch, in relity, the divisions will be imperfect. The most probble fult in the resistor ldder is tht the vlue of resistor exceeds its tolernce bnd (prmetric fult). These fults cn be detected by the mesurement nd evlution of current vlue in the respective current brnches. The described technique hs been used for prmetric test of the -2 ldder, which represent substntil prt of the whole DAC circuit. Modifiction of this method, used in digitl IC test, is known s I DDQ testing. Principle of current testing of the -2 ldder is s follows: in the first step, current I8 is compred to the sum of currents I7 to I0, then in the second step, the control logic turnsoff switches S8 nd S8, nd current I7 is compred to the sum of currents I6 to I0. Consequently, control logic turns-off switches S7 nd S7, nd nother two currents re compred. where N = 1, 2, 3,... 8 nd IN is current in the respective brnch being sensed. Circuit digrm of -2 ldder with the dditionl test hrdwre is depicted in Fig. 8. In every brnch of the resistive network, two T-gtes were included to switch-off the corresponding brnch. Control signls for T-gtes (, nd lso 1-8 ) were generted by the common control logic. Circuitry performing the current difference consists of three cscode current mirrors, s shown in Fig. 8 (right side). This circuit lso ensures tht the differentil current (difference of I EF 1 nd I EF 2 ) will flow out to the circuit s output. This pproch cn test the resistor ldder in totl eight steps, by shifting the logic 1 from MBS to LSB. The min problem of this method is tht current in the lst brnch is in order of na, which is difficult to sense nd mesure with necessry precision. Therefore, this test technique might be limited to ldders tht use resistors with the resistnce vlue smller thn 10kΩ. A fult-free tolernce bnd of the differentil current I diff ws obtined by Monte Crlo nlysis nd chieved results will be presented in the following section. V EF I 8 I 7 I 1 I 0 M11 M12 V VSS_EF I EF1 I EF2 M3 M9 M4 M7 M10 M8 I DIFF M1 M2 M5 M6 LATCH LATCH LATCH CL LOAD D_IN CL LOAD D_IN CL LOAD D_IN CUENT DIFFEENTIAL CICUIT CL LOAD -2 LADDE D7 D6 D0 Fig. 8. Circuit digrm of -2 ldder with dditionl test hrdwre (without control logic)
5 V. INFLUENCE OF ADDITIONAL TEST HADWAE Insertion of the necessry on-chip test hrdwre might undesirbly ffect the DAC performnce. The min reson is probbly the use of T-gtes (disconnecting the individul prts), which hve some resistnce in switch-on stte. The most criticl re T-gtes tht re connected in the pth leding to the circuit output. Fig. 9 shows how the integrl nd the differentil nonlinerity (INL nd DNL ) of the DAC (with the test hrdwre) depend on the ON resistnce of T-gtes connected in the pth leding to the converter output INL' DNL' SN [db] Fig. 11. Signl to Noise tio Efective Number of Bits k 10k ON_T-gte [Ω] SN nd ENOB versus ON of T-gte ENOB 9.0 INL' Fig on_t-gte [Ω] INL nd DNL versus ON of T-gte It cn be observed tht in order to mintin the originl prmeters of DAC, ON of T-gtes should be order of tens of Ohms. If the T-gtes with ON of bout 10 Ω re used, the vlue of integrl nd differentil nonlinerity will be incresed by 18% nd 27%, respectively. In such cse, the dditionl test hrdwre will require the re of mm 2, which mens tht the totl re will be enlrged by 13%. From the spect of testing it is therefore, necessry to find good compromise between the CUT performnce nd the test hrdwre re overhed. Fig. 10 nd Fig. 11 show how the other min prmeters of the digitl-to-nlog converter (with the dditionl test hrd- OE, FSE, GE [V] Fig m 140.0m 120.0m 100.0m 80.0m offset error (OE) full scle error (FSE) gin error (GE) 60.0m 40.0m 20.0m m -40.0m -60.0m -80.0m m m m m k 10k ON_T-gte [Ω] OE, FSE nd GE versus ON of T-gte DNL' wre) depend on the switch-on resistnce of T-gtes connected in pth leding to the converter output. It cn be observed tht to mintin the originl vlue of the full scle error (FSE), signl-to-noise rtion (SN) nd effective number of bits (ENOB) prmeters, it would be sufficient to use T-gte with ON of bout 100 Ω. However, chieve the originl vlues of INL, DNL, offset error (OE) nd gin error (GE), ON should be bout of tens of Ohms. Thus, it cn be concluded tht to mintin the originl vlue of ll prmeters of the converter, ON of T-gtes should be kept in the rnge from 10 to 100 Ohms. In this cse, the totl re overhed would be enlrged from 6.5% to 13%. VI. ACHIEVED ESULTS For verifiction of the efficiency of the proposed test methods in testing prts of DACs, four types of ctstrophic fults in the OPAMP, nd two prmetric fults in the - 2 ldder were considered. Ctstrophic fults such s shorts, opens, gte-oxide shorts (GOS) nd floting gtes (FG) were inserted. Short nd open fults were injected in ll connection pths, while GOS nd FG fults were pplied in ll trnsistors forming the OPAMP. Prmetric fults, which most commonly rise on pssive devices, were modeled nd injected in the - 2 resistor network. A. esults of the opertionl mplifier test In the opertionl mplifier, severl ctstrophic fults such s opens nd shorts s well s floting gtes nd gte-oxideshorts, were considered. For their detection, the oscilltionbsed test method of the OPAMP circuit ws employed. Opens were modeled using prllel combintion of resistor nd cpcitor. esistors nd cpcitors vlues depend on the defect loction nd size. We hve considered nine different open fults injected in 24 different loctions. From ll considered 216 opens, 209 fults were detected, which mens tht the fult coverge of 94% ws chieved. However, opens modeled with the resistnce vlue of 1 MΩ represent so cll hrd-detectble fults. Thus, opens hving higher resistnce would probbly not be covered by other test technique either.
6 Short fults were modeled nd simulted using seril short resistor. Vlues of resistors considered s short fults re s follows: 500 Ω, 1kΩ, 10k Ω, 100 kω nd 1 MΩ. The chieved fult coverge, presented for different rnges of the short resistnce vlue, is presented in Tble I. TABLE I FAULT COVEAGE OF SHOT FAULTS short [Ω] k k 500 1M Fult Coverge 100% 95.58% 84.7% It cn be observed tht shorts with lower resistnce re esier to detect becuse, in most cses, such shorts led to loss of the oscilltions or significnt devition in the mplitude of oscilltions. Shorts with the resistnce higher thn 100 kω usully cuse only slight devition in the oscilltion frequency tht mkes them more difficult to detect. For floting gtes (FG) we used n extended electricl model described in [27], considering lso cpcity of the brek. Hence, the FG fult model includes cpcitors C mp, C pb nd C brek, which vlues were set to 2.82 ff, 3.02 ff nd 0.07 ff, respectively. All considered FG fults were esily detected through either loss of the oscilltion or chnge in the oscilltion frequency (single fult). The worst cse of the overll fult coverge of ll ctstrophic fults, using the externl oscilltor feedbck network, is summrized in Tble II. TABLE II WOST CASE OF OFF-CHIP TOTAL FAULT COVEAGE Fults Fult coverge Shorts 84.7% Opens 94% FGs 100% Totl 92.9% The totl fult coverge chieved for on-chip reliztion of the proposed prmetric test of the OPAMP block is summrized in Tble III. TABLE III TOTAL FAULT COVEAGE FO ON-CHIP TEST OF OPAMP different ctstrophic fults (including hrd-detectble ones) in nlog sub-circuits. We lso nlyzed the possible dependence of the fult coverge in the OPAMP on the vlue of the oscilltion frequency. To test the mplifier by oscilltion-bsed strtegy t different oscilltion frequencies, the vlue of pssive devices used in the positive feedbck loop ws vried. The fult coverge dependence on the vlue of the oscilltion frequency for different shorts nd floting gtes is shown in Fig. 12 nd Fig. 13, respectively. FC [%] Short resistnce 500Ohm 1kOhm 10kOhm 100kOhm 1MOhm M 4.0M 6.0M 8.0M f osc [Hz] Fig. 12. Fult coverge versus the vlue of the oscilltion frequency for different shorts One cn observe tht the best fult coverge cn be chieved t the oscilltion frequency of bout 2 MHz. Shorts with lower resistnce re esy to detect since they usully cuse loss of oscilltions. Shorts with higher resistnce (e.g. of 100 kω, 1 MΩ) cuse devition from the oscillting frequency, which 100 Fults inserted detected Fult coverge Shorts % Opens % FGs % Totl % FC [%] The off-chip pproch offers slightly higher totl fult coverge thn the one chieved in cse of on-chip test reliztion. On the other hnd, on-chip pproch enbles BIST tht is typicl for SoC testing. However, some of the undetected fults hve been mnifested by certin devition in the mplitude of oscilltions (not evluted in our experiment). Therefore, the totl fult coverge might be incresed further by evlution of this prmeter. The obtined results prove tht the oscilltionbsed test pproch cn be reltively very efficient in detecting 80 FC for floting gte fults 75 0,0 2,0M 4,0M 6,0M 8,0M f OSC [Hz] Fig. 13. Fult coverge versus the oscilltion frequency vlue for floting gte fults
7 mkes them more difficult to detect. Generlly, the shorts with lower short resistnce re esily detectble t lower oscilltion frequencies, while the shorts with higher resistnce (in order of 100 kω) re better covered t the higher frequency (bout 4.5 MHz). Finlly, shorts with resistnce of 1 MΩ hve lowest fult coverge in whole frequency rnge but those fults hve low probbility of presence. Secondly, the fult coverge dependence on the vlue of the oscilltion frequency for floting gte fults ws investigted (Fig. 13). It cn be observed tht 100% fult coverge cn be chieved for the vlue of the oscilltion frequency of 3 MHz nd lso for vlues higher thn 8 MHz. Unfortuntely, for the frequency higher thn 8.5 MHz the CUT does not fulfill the conditions needed for the ppernce of sustined oscilltions. B. esults of -2 ldder test In contrst to the OPAMP test, prmetric fults were considered in the resistor network (-2 ldder), nd the fult coverge by the proposed current test method ws investigted. Possible prmetric fults in the resistor network were simulted using resistor with vrying its resistnce vlue. It ws considered tht the vlue devites by 5% or 10% from the tolernce rnge. Fig. 14 shows the tolernce bnd nd simulted vlues of the output differentil current depending on the test vector being pplied. I diff [ua] TOLEANCE BAND Test vector -5% +5% -10% +10% I_min I_mx Fig. 14. Tolernce bnd nd simulted vlues of the differentil current in -2 ldder The simultion results show tht lmost ll prmetric fults in the resistor network re detectble. However, prmetric fult considered in the lst brnch is difficult to detect becuse the current is too smll to be sensed precisely. Tble IV shows the fult coverge chieved by current monitoring pproch for prmetric fults considered in the resistor network. It cn be observed tht 10% devition in resistors vlue is fully detectble nd 100% fult coverge is reched. When the resistors vlue devites from its tolernce bnd by 5%, the fult coverge is slightly lowered to 96% tht is still very good result. Finlly, we cn stte tht the proposed current test method is esy to implement nd provides very high efficiency in TABLE IV FAULT COVEAGE OF SHOT FAULTS Prmetric fult ±5% devition ±10% devition Fult Coverge 96% 100% covering prmetric fults. However, the method might be limited by resistnce vlues of resistors used in the ldder, since high vlues led to less current flowing through the respective brnches, which is rther difficult to be mesured nd processed. VII. DISCUSSION &CONCLUSION Two different prmetric test methods hve been used for on-chip fult detection in the -2 ldder digitl-to-nlog converter. For this purpose, n experimentl circuit, consisting of the DAC, the dditionl test hrdwre, nd the control logic for switching the DAC between functionl nd test modes, hs been designed in selected CMOS technology. The control logic ws used to split the circuit into two prts, ech tested seprtely by dedicted method. An opertionl mplifier ws tested by the oscilltion-bsed test strtegy, while current monitoring ws used to test the resistor ldder. The crucil point of the used test strtegy is tht the insertion of the necessry dditionl test hrdwre might ffect the CUT performnce. However, with pproprite setting of ON of the inserted T-gtes, this influence cn be minimized. T-gtes with ON of bout 10 Ω cuse re overhed of 13%, nd increse of 18% nd 27% in INL nd DNL prmeters, respectively. Ctstrophic nd prmetric fults were considered in the CUT. In the worst cse, the totl fult coverge of 92.42% nd 96% for the OPAMP nd the resistor network ws chieved, respectively. This is n excellent result especilly, if tking into ccount tht the fult coverge up to 94.21% of hrddetectble fults by prmetric test of single prts of the DAC hs been chieved. The on-chip totl fult coverge might be incresed by mesuring the mplitude of oscilltion. However, for evlution of the mplitude of oscilltion, the dditionl test hrdwre will be necessry, which would increse the re overhed. On-chip prmetric test of seprted prts is promising strtegy to test complex mixed-signl systems. This pproch offers the possibility to identify defective prt nd mkes test of such systems esier or, in some pplictions, even possible t ll. However, it is necessry to mintin the circuit s originl functionlity nd specific prmeters. Further reserch in this field will be focused on reliztion of BIST structures, bsed on the oscilltion test strtegy, which would be generlly pplicble for digitl-to-nlog converters s cores used in complex SoCs. ACKNOWLEDGMENT This work ws supported in prt by the Ministry of Eduction, Science, eserch nd Sport of the Slovk epublic under grnts VEGA 1/0285/09, VEGA 1/1008/12, VMSP-II APVV nd the Centre of Excellence for Smrt Technology, Systems nd Services II, ITMS Code Authors lso thnk -DAS, s.r.o for reserch support.
8 EFEENCES [1] T. Jeng-Horng, M.-J. Hsio, nd T.-. Chng, An embedded built-inself-test pproch for digitl-to-nlog converters, in Test Symposium, Proceedings. 10th Asin, 2001, pp [2] M. H., Test requirements for todys nd future circuits: A perspective, in Proceedings of Electronic circuits nd Systems, 2005, pp [3] J. L. H. Diz, Test nd Design-for-Testbility in Mixed-Signl Integrted Circuits, 1st ed. Springer, October 2004, no [4] J. Wibbenmeyer nd C.-I. Chen, Built-in self-test for low-voltge highspeed nlog-to-digitl converters, Instrumenttion nd Mesurement, IEEE Trnsctions on, vol. 56, no. 6, pp , dec [5] H. Xing, H. Jing, D. Chen, nd. Geiger, High-resolution ADC linerity testing using fully digitl-comptible BIST strtegy, Instrumenttion nd Mesurement, IEEE Trnsctions on, vol. 58, no. 8, pp , ug [6] K. Arbi, I. Kminsk, nd J. zeszut, BIST for D/A nd A/D converters, Design Test of Computers, IEEE, vol. 13, no. 4, pp , winter [7] IEEE drft stndrd for terminology nd test methods of digitl-tonlog converter devices, IEEE P1658/D8.8, June 2011, pp , [8] K. Arbi, B. Kminsk, nd M. Swn, On chip testing dt converters using sttic prmeters, Very Lrge Scle Integrtion (VLSI) Systems, IEEE Trnsctions on, vol. 6, no. 3, pp , sept [9] J. mesh, M. Srinivsulu, nd K. Gunvthi, A novel on chip circuit for fult detection in digitl to nlog converters, in Control, Automtion, Communiction nd Energy Conservtion, INCACEC Interntionl Conference on, june 2009, pp [10] J.-L. Hung, C.-K. Ong, nd K.-T. Cheng, A BIST scheme for onchip ADC nd DAC testing, in Design, Automtion nd Test in Europe Conference nd Exhibition Proceedings, 2000, pp [11] K. Arbi, B. Kminsk, nd J. zeszut, A new built-in self-test pproch for digitl-to-nlog nd nlog-to-digitl converters, in Computer-Aided Design, 1994., IEEE/ACM Interntionl Conference on, nov 1994, pp [12] E. Terok, T. Kengku, I. sui, K. Ishikw, T. Mtsuo, H. Wkd, N. Skshit,. Shimzu, nd T. Tokud, A built-in self-test for ADC nd DAC in single-chip speech CODEC, in Test Conference, Proceedings., Interntionl, oct 1993, pp [13] C. W. Lin, S. F. Lin, nd S. F. Luo, A new pproch for nonlinerity test of high speed DAC, in Mixed-Signls, Sensors, nd Systems Test Workshop, IMS3TW IEEE 14th Interntionl, june 2008, pp [14] C. W. Lin nd S. F. Lin, A BIST scheme for testing DAC, in Electricl Engineering/Electronics, Computer, Telecommunictions nd Informtion Technology (ECTI-CON), th Interntionl Conference on, my 2012, pp [15] B. Kminsk nd K. Arbi, Mixed signl DFT: concise overview, in Computer Aided Design, ICCAD Interntionl Conference on, nov. 2003, pp [16] E. J. Perls, A. ued, nd J. L. Huerts, New BIST schemes for structurl testing of pipelined nlog to digitl converters, Journl of Electronic Testing, vol. 17, pp , 2001, /A: [Online]. Avilble: [17]. Jun nd T. Msyoshi, A BIST scheme bsed on resistnce mtch for current-mode -2 ldder digitl-to-nlog converter, in Computer eserch nd Development (ICCD), rd Interntionl Conference on, vol. 3, mrch 2011, pp [18] K. Arbi nd B. Kminsk, Prmetric nd ctstrophic fult coverge of nlog circuits in oscilltion-test methodology, in VLSI Test Symposium, 1997., 15th IEEE, pr-1 my 1997, pp [19] G. H. Snchez, V. G. D. L. V. Diego, nd. Adorcisn, Oscilltion- Bsed Test in Mixed-Signl Circuits (Frontiers in Electronic Testing). Secucus, NJ, USA: Springer-Verlg New ork, Inc., [20] K. Arbi nd B. Kminsk, Oscilltion-test strtegy for nlog nd mixed-signl integrted circuits, in VLSI Test Symposium, 1996., Proceedings of 14th, pr-1 my 1996, pp [21] D. Arbet, J. Brenkus, G. Gyepes, nd V. Stopjkov, Incresing the efficiency of nlog OBIST using on-chip compenstion of technology vritions, in Design nd Dignostics of Electronic Circuits Systems (DDE), 2011 IEEE 14th Interntionl Symposium on, pril 2011, pp [22]. jsumn, Iddq testing for CMOS VLSI, Proceedings of the IEEE, vol. 88, no. 4, pp , pril [23] S. Bhuni, H. Li, nd K. oy, A high performnce IDDQ testble cche for scled CMOS technologies, in Test Symposium, (ATS 02). Proceedings of the 11th Asin, nov. 2002, pp [24]. jsumn, Design-for-iddq-testing for embedded cores bsed system-on--chip, in IDDQ Testing, Proceedings IEEE Interntionl Workshop on, nov 1998, pp [25] V. Stopjkov nd H. Mnheve, CCII+ current conveyor bsed BIC monitor for IDDQ testing of complex CMOS circuits, in Europen Design nd Test Conference, ED TC 97. Proceedings, mr 1997, pp [26] K. Arbi nd B. Kminsk, Oscilltion built-in self test (OBIST) scheme for functionl nd structurl testing of nlog nd mixed-signl integrted circuits, in Test Conference, Proceedings., Interntionl, nov 1997, pp [27] A. M. Bros nd J. Figuers, Chrcteriztion of floting gte defects in nlog cells, Journl of Electronic Testing, vol. 14, pp , 1999, /A: [Online]. Avilble: Dniel Arbet received the M.S. degree in Electronics from Slovk University of Technology in Brtislv, Slovki in Since October 2009 he hs been PhD student t the Institute of Electronics nd Photonics of Slovk University of Technology. He hs published more thn 10 ppers. His min reserch interests re low-voltge low-power nlog design, on-chip prmetric testing, nlog BIST nd test implementtion. Vier Stopjková received the M.S. degree nd the PhD degree in Electronics from Slovk University of Technology in Brtislv, Slovki, in 1992, nd 1997, respectively. From October 1997 to September 2003 nd from October 2003 to June 2009 she ws n ssistnt professor nd n ssocited professor t Microelectronics Deprtment, Fculty of Electricl Engineering nd Informtion Technology of Slovk University of Technology in Brtislv, respectively. Currently, she is full professor t the Institute of Electronics nd Photonics of the sme university. She hs been involved in severl EU funded reserch projects under different funding schemes such s TEMPUS, ESPIT, Copernicus, FP, ENIAC-JU, nd lso in ntionl reserch grnts. She hs published over 90 ppers in vrious journls nd conference proceedings; nd she is co-inventor of two US ptents in the field of on-chip supply current testing. Her min reserch interests include IC design, VLSI & SoC testing, on-chip testing, design nd test of mixed-signl circuits, biomedicl monitoring, nd neurl network implementtions nd pplictions. Jurj Brenkuš received the M.S. degree in Electronics from Slovk University of Technology in Brtislv, Slovki in Since Mrch 2010 he hs been resercher t Institute of Electronics nd Photonics of Slovk University of Technology. He is the uthor or co-uthor of more thn 20 ppers presented t interntionl conferences. His min reserch interests re IC design nd test, mixedsignl systems design, SoC design, on-chip testing nd test development utomtion. Gábor Gyepes received the M.S. degree in Electronics from Slovk University of Technology in Brtislv, Slovki in Since October 2009 he hs been PhD student t the Institute of Electronics nd Photonics of Slovk University of Technology. His min reserch interests include nlog IC design, memory test nd on-chip current testing. He hs published more thn 10 ppers in these res.
Experiment 3: Non-Ideal Operational Amplifiers
Experiment 3: Non-Idel Opertionl Amplifiers Fll 2009 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output
More informationCHAPTER 2 LITERATURE STUDY
CHAPTER LITERATURE STUDY. Introduction Multipliction involves two bsic opertions: the genertion of the prtil products nd their ccumultion. Therefore, there re two possible wys to speed up the multipliction:
More informationExperiment 3: Non-Ideal Operational Amplifiers
Experiment 3: Non-Idel Opertionl Amplifiers 9/11/06 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output
More informationApplication Note. Differential Amplifier
Appliction Note AN367 Differentil Amplifier Author: Dve n Ess Associted Project: Yes Associted Prt Fmily: CY8C9x66, CY8C7x43, CY8C4x3A PSoC Designer ersion: 4. SP3 Abstrct For mny sensing pplictions, desirble
More informationUnderstanding Basic Analog Ideal Op Amps
Appliction Report SLAA068A - April 2000 Understnding Bsic Anlog Idel Op Amps Ron Mncini Mixed Signl Products ABSTRACT This ppliction report develops the equtions for the idel opertionl mplifier (op mp).
More informationFuzzy Logic Controller for Three Phase PWM AC-DC Converter
Journl of Electrotechnology, Electricl Engineering nd Mngement (2017) Vol. 1, Number 1 Clusius Scientific Press, Cnd Fuzzy Logic Controller for Three Phse PWM AC-DC Converter Min Muhmmd Kml1,, Husn Ali2,b
More informationABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC
User Mnul ntelligent nstlltion Systems A B 1 2 3 4 5 6 7 8 30 ma 30 ma n = AC Un = 230 V AC 30 ma 9 10 11 12 C ABB STOTZ-KONTAKT Appliction Softwre Current Vlue Threshold/1 Contents Pge 1 Device Chrcteristics...
More informationMixed CMOS PTL Adders
Anis do XXVI Congresso d SBC WCOMPA l I Workshop de Computção e Aplicções 14 20 de julho de 2006 Cmpo Grnde, MS Mixed CMOS PTL Adders Déor Mott, Reginldo d N. Tvres Engenhri em Sistems Digitis Universidde
More informationMAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES
MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES Romn V. Tyshchuk Informtion Systems Deprtment, AMI corportion, Donetsk, Ukrine E-mil: rt_science@hotmil.com 1 INTRODUCTION During the considertion
More informationSimulation of Transformer Based Z-Source Inverter to Obtain High Voltage Boost Ability
Interntionl Journl of cience, Engineering nd Technology Reserch (IJETR), olume 4, Issue 1, October 15 imultion of Trnsformer Bsed Z-ource Inverter to Obtin High oltge Boost Ability A.hnmugpriy 1, M.Ishwry
More informationCHAPTER 3 AMPLIFIER DESIGN TECHNIQUES
CHAPTER 3 AMPLIFIER DEIGN TECHNIQUE 3.0 Introduction olid-stte microwve mplifiers ply n importnt role in communiction where it hs different pplictions, including low noise, high gin, nd high power mplifiers.
More informationStudy on SLT calibration method of 2-port waveguide DUT
Interntionl Conference on Advnced Electronic cience nd Technology (AET 206) tudy on LT clibrtion method of 2-port wveguide DUT Wenqing Luo, Anyong Hu, Ki Liu nd Xi Chen chool of Electronics nd Informtion
More informationThis is a repository copy of Effect of power state on absorption cross section of personal computer components.
This is repository copy of Effect of power stte on bsorption cross section of personl computer components. White Rose Reserch Online URL for this pper: http://eprints.whiterose.c.uk/10547/ Version: Accepted
More information(CATALYST GROUP) B"sic Electric"l Engineering
(CATALYST GROUP) B"sic Electric"l Engineering 1. Kirchhoff s current l"w st"tes th"t (") net current flow "t the junction is positive (b) Hebr"ic sum of the currents meeting "t the junction is zero (c)
More informationA Novel Back EMF Zero Crossing Detection of Brushless DC Motor Based on PWM
A ovel Bck EMF Zero Crossing Detection of Brushless DC Motor Bsed on PWM Zhu Bo-peng Wei Hi-feng School of Electricl nd Informtion, Jingsu niversity of Science nd Technology, Zhenjing 1003 Chin) Abstrct:
More informationEET 438a Automatic Control Systems Technology Laboratory 5 Control of a Separately Excited DC Machine
EE 438 Automtic Control Systems echnology bortory 5 Control of Seprtely Excited DC Mchine Objective: Apply proportionl controller to n electromechnicl system nd observe the effects tht feedbck control
More informationA Development of Earthing-Resistance-Estimation Instrument
A Development of Erthing-Resistnce-Estimtion Instrument HITOSHI KIJIMA Abstrct: - Whenever erth construction work is done, the implnted number nd depth of electrodes hve to be estimted in order to obtin
More informationDesign And Implementation Of Luo Converter For Electric Vehicle Applications
Design And Implementtion Of Luo Converter For Electric Vehicle Applictions A.Mnikndn #1, N.Vdivel #2 ME (Power Electronics nd Drives) Deprtment of Electricl nd Electronics Engineering Sri Shkthi Institute
More informationThe Discussion of this exercise covers the following points:
Exercise 4 Bttery Chrging Methods EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the different chrging methods nd chrge-control techniques commonly used when chrging Ni-MI
More informationDESIGN OF CONTINUOUS LAG COMPENSATORS
DESIGN OF CONTINUOUS LAG COMPENSATORS J. Pulusová, L. Körösi, M. Dúbrvská Institute of Robotics nd Cybernetics, Slovk University of Technology, Fculty of Electricl Engineering nd Informtion Technology
More informationEngineer-to-Engineer Note
Engineer-to-Engineer Note EE-236 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our
More informationISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.5
21.5 A 1.1GHz Chrge-Recovery Logic Visvesh Sthe, Jung-Ying Chueh, Mrios Ppefthymiou University of Michign, Ann Aror, MI Boost Logic is chrge-recovery circuit fmily cple of operting t GHz-clss frequencies
More informationExercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION
Exercise 1-1 The Sine Wve EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the notion of sine wve nd how it cn be expressed s phsor rotting round the center of circle. You
More informationSynchronous Machine Parameter Measurement
Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions
More informationSynchronous Machine Parameter Measurement
Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions
More informationRobustness Analysis of Pulse Width Modulation Control of Motor Speed
Proceedings of the World Congress on Engineering nd Computer Science 2007 WCECS 2007, October 24-26, 2007, Sn Frncisco, USA obustness Anlysis of Pulse Width Modultion Control of Motor Speed Wei Zhn Abstrct
More informationDirect AC Generation from Solar Cell Arrays
Missouri University of Science nd Technology Scholrs' Mine UMR-MEC Conference 1975 Direct AC Genertion from Solr Cell Arrys Fernndo L. Alvrdo Follow this nd dditionl works t: http://scholrsmine.mst.edu/umr-mec
More informationA New Stochastic Inner Product Core Design for Digital FIR Filters
MATEC Web of Conferences, (7) DOI:./ mtecconf/7 CSCC 7 A New Stochstic Inner Product Core Design for Digitl FIR Filters Ming Ming Wong,, M. L. Dennis Wong, Cishen Zhng, nd Ismt Hijzin Fculty of Engineering,
More informationPostprint. This is the accepted version of a paper presented at IEEE PES General Meeting.
http://www.div-portl.org Postprint This is the ccepted version of pper presented t IEEE PES Generl Meeting. Cittion for the originl published pper: Mhmood, F., Hooshyr, H., Vnfretti, L. (217) Sensitivity
More informationHigh Speed On-Chip Interconnects: Trade offs in Passive Termination
High Speed On-Chip Interconnects: Trde offs in Pssive Termintion Rj Prihr University of Rochester, NY, USA prihr@ece.rochester.edu Abstrct In this pper, severl pssive termintion schemes for high speed
More informationDYE SOLUBILITY IN SUPERCRITICAL CARBON DIOXIDE FLUID
THERMAL SCIENCE, Yer 2015, Vol. 19, No. 4, pp. 1311-1315 1311 DYE SOLUBILITY IN SUPERCRITICAL CARBON DIOXIDE FLUID by Jun YAN, Li-Jiu ZHENG *, Bing DU, Yong-Fng QIAN, nd Fng YE Lioning Provincil Key Lbortory
More informationThreshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication
1 Threshold Logic Computing: Memristive-CMOS Circuits for Fst Fourier Trnsform nd edic Multipliction Alex Pppchen Jmes, Dinesh S. Kumr, nd Arun Ajyn Abstrct Brin inspired circuits cn provide n lterntive
More informationPB-735 HD DP. Industrial Line. Automatic punch and bind machine for books and calendars
PB-735 HD DP Automtic punch nd bind mchine for books nd clendrs A further step for the utomtion of double loop binding. A clever nd flexible mchine ble to punch nd bind in line up to 9/16. Using the best
More informationTo provide data transmission in indoor
Hittite Journl of Science nd Engineering, 2018, 5 (1) 25-29 ISSN NUMBER: 2148-4171 DOI: 10.17350/HJSE19030000074 A New Demodultor For Inverse Pulse Position Modultion Technique Mehmet Sönmez Osmniye Korkut
More informationMETHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN. Inventor: Brian L. Baskin
METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN Inventor: Brin L. Bskin 1 ABSTRACT The present invention encompsses method of loction comprising: using plurlity of signl trnsceivers to receive one or
More informationInterference Cancellation Method without Feedback Amount for Three Users Interference Channel
Open Access Librry Journl 07, Volume, e57 ISSN Online: -97 ISSN Print: -9705 Interference Cncelltion Method without Feedbc Amount for Three Users Interference Chnnel Xini Tin, otin Zhng, Wenie Ji School
More informationA Simple Approach to Control the Time-constant of Microwave Integrators
5 VOL., NO.3, MA, A Simple Approch to Control the Time-constnt of Microwve Integrtors Dhrmendr K. Updhyy* nd Rkesh K. Singh NSIT, Division of Electronics & Communiction Engineering New Delhi-78, In Tel:
More informationNevery electronic device, since all the semiconductor
Proceedings of Interntionl Joint Conference on Neurl Networks, Orlndo, Florid, USA, August 12-17, 2007 A Self-tuning for Rel-time Voltge Regultion Weiming Li, Xio-Hu Yu Abstrct In this reserch, self-tuning
More information(1) Non-linear system
Liner vs. non-liner systems in impednce mesurements I INTRODUCTION Electrochemicl Impednce Spectroscopy (EIS) is n interesting tool devoted to the study of liner systems. However, electrochemicl systems
More informationModeling of Conduction and Switching Losses in Three-Phase Asymmetric Multi-Level Cascaded Inverter
Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp176-181) Modeling of onduction nd witching Losses in Three-Phse Asymmetric Multi-Level
More informationMulti-beam antennas in a broadband wireless access system
Multi-em ntenns in rodnd wireless ccess system Ulrik Engström, Mrtin Johnsson, nders Derneryd nd jörn Johnnisson ntenn Reserch Center Ericsson Reserch Ericsson SE-4 84 Mölndl Sweden E-mil: ulrik.engstrom@ericsson.com,
More informationThe computer simulation of communication for PLC systems
The computer simultion of communiction for PLC systems Jiri Misurec Milos Orgon Dept. of Telecommunictions Fculty of Electricl Engineering nd Communiction Brno University of Technology Purkynov 8 6 00
More informationRedundancy Data Elimination Scheme Based on Stitching Technique in Image Senor Networks
Sensors & Trnsducers 204 by IFSA Publishing, S. L. http://www.sensorsportl.com Redundncy Dt Elimintion Scheme Bsed on Stitching Technique in Imge Senor Networks hunling Tng hongqing Technology nd Business
More informationCompared to generators DC MOTORS. Back e.m.f. Back e.m.f. Example. Example. The construction of a d.c. motor is the same as a d.c. generator.
Compred to genertors DC MOTORS Prepred by Engr. JP Timol Reference: Electricl nd Electronic Principles nd Technology The construction of d.c. motor is the sme s d.c. genertor. the generted e.m.f. is less
More informationMULTILEVEL INVERTER TOPOLOGIES USING FLIPFLOPS
MULTILVL INVRTR TOPOLOGIS USING FLIPFLOPS C.R.BALAMURUGAN S.SIVASANKARI Aruni ngineering College, Tiruvnnmli. Indi crblin010@gmil.com, sivyokesh1890@gmil.com S.P.NATARAJAN Annmli University, Chidmbrm,
More informationLow noise SQUID simulator with large dynamic range of up to eight flux quanta
Low noise SQUID simultor with lrge dynmic rnge of up to eight flux qunt A. Mrtinez*, J. Flokstr, C. Rillo**, L.A. Angurel**, L.M. Grci** nd H.J.M. ter Brke Twente University of Technology, Deprtment of
More informationEliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses
Eliminting Non-Determinism During of High-Speed Source Synchronous Differentil Buses Abstrct The t-speed functionl testing of deep sub-micron devices equipped with high-speed I/O ports nd the synchronous
More informationOSCILLATION-BASED TEST APPLIED TO DIGITAL SPECTROMETERS
OSCILLATION-BASED TEST APPLIED TO DIGITAL SPECTROMETERS Gbriel Peretti (, Edurdo Romero (, Crlos Mrqués (2 ( Grupo de Investigción y Servicios en Electrónic y Control. Fcultd Regionl Vill Mrí. Universidd
More informationOpen Access A Novel Parallel Current-sharing Control Method of Switch Power Supply
Send Orders for Reprints to reprints@enthmscience.e 170 The Open Electricl & Electronic Engineering Journl, 2014, 8, 170-177 Open Access A Novel Prllel Current-shring Control Method of Switch Power Supply
More informationEffect of High-speed Milling tool path strategies on the surface roughness of Stavax ESR mold insert machining
IOP Conference Series: Mterils Science nd Engineering PAPER OPEN ACCESS Effect of High-speed Milling tool pth strtegies on the surfce roughness of Stvx ESR mold insert mchining Relted content - Reserch
More informationScienceDirect. Adaptive LMS Filter using in Flexible Mechatronics System with Variable Parameter Control
Avilble online t www.sciencedirect.com ScienceDirect Procedi Engineering 69 ( 014 ) 33 33 4th DAAA Interntionl Symposium on Intelligent nufcturing nd Automtion, 013 Adptive S Filter using in Flexible echtronics
More informationPassive and Active Hybrid Integrated EMI Filters
Pssive nd Active Hybrid Integrted EMI Filters J. Biel, A. Wirthmueller, R. Wespe, M.. Heldwein, J. W. Kolr Power Electronic Systems bortory Swiss Federl Institute of Technology Zurich, Switzerlnd Emil:
More informationProducts no longer available
echnicl dt sheet otry ctutor F2-P(-O) ultifunctionl rotry ctutor with emergency control for 2 nd 3 wy control bll vlve orque Nm Nominl voltge C/DC 2 V Control: odulting DC... V or vrible Position feedbck
More informationCS 135: Computer Architecture I. Boolean Algebra. Basic Logic Gates
Bsic Logic Gtes : Computer Architecture I Boolen Algebr Instructor: Prof. Bhgi Nrhri Dept. of Computer Science Course URL: www.ses.gwu.edu/~bhgiweb/cs35/ Digitl Logic Circuits We sw how we cn build the
More informationModeling of Inverter Fed Five Phase Induction Motor using V/f Control Technique
Interntionl Journl of Current Engineering nd Technology E-ISSN 2277 4106, P-ISSN 2347 161 201INPRESSCO, All Rights Reserved Avilble t http://inpressco.com/ctegory/ijcet Reserch Article Modeling of Inverter
More informationEngineer-to-Engineer Note
Engineer-to-Engineer Note EE-297 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors or e-mil
More informationPerformance Comparison of Sliding Mode Control and Conventional PI Controller for Speed Control of Separately Excited Direct Current Motors
Journl of Science nd Technology Vol. 13, No. 2 Engineering nd Computer Sciences (ECS) Performnce Comprison of Sliding Mode Control nd Conventionl PI Controller for Speed Control of Seprtely Excited Direct
More informationV O = a(v I - V B ) (EQ. 10) V B = V O Z 1 / (Z 1 + Z 2 ), I B = 0 (EQ. 11) V O = av I - az 1 V O / (Z 1 + Z 2 ) (EQ. 12)
APPLICATION NOTE Feedbck, Op Amps nd AN9415 Rev. 3.00 Introduction There re mny benefits [1] which result from the use of feedbck in electronic circuits, but the drwbcks re the incresed complexity of the
More informationLab 8. Speed Control of a D.C. motor. The Motor Drive
Lb 8. Speed Control of D.C. motor The Motor Drive Motor Speed Control Project 1. Generte PWM wveform 2. Amplify the wveform to drive the motor 3. Mesure motor speed 4. Mesure motor prmeters 5. Control
More informationSystem-Wide Harmonic Mitigation in a Diesel Electric Ship by Model Predictive Control
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS System-Wide Hrmonic Mitigtion in Diesel Electric Ship by Model Predictive Control Espen Skjong, Jon Are Suul, Member, IEEE, Atle Rygg, Tor Arne Johnsen, Senior
More informationResearch on Local Mean Decomposition Algorithms in Harmonic and Voltage Flicker Detection of Microgrid
Sensors & Trnsducers 23 by IFSA http://www.sensorsportl.com Reserch on Locl Men Decomposition Algorithms in Hrmonic nd Voltge Flicer Detection of Microgrid Wensi CAO, Linfei LIU School of Electric Power,
More informationExponential-Hyperbolic Model for Actual Operating Conditions of Three Phase Arc Furnaces
Americn Journl of Applied Sciences 6 (8): 1539-1547, 2009 ISSN 1546-9239 2009 Science Publictions Exponentil-Hyperbolic Model for Actul Operting Conditions of Three Phse Arc Furnces 1 Mhdi Bnejd, 2 Rhmt-Allh
More informationECE 274 Digital Logic. Digital Design. Datapath Components Shifters, Comparators, Counters, Multipliers Digital Design
ECE 27 Digitl Logic Shifters, Comprtors, Counters, Multipliers Digitl Design..7 Digitl Design Chpter : Slides to ccompny the textbook Digitl Design, First Edition, by Frnk Vhid, John Wiley nd Sons Publishers,
More informationDiscontinued AN6262N, AN6263N. (planed maintenance type, maintenance type, planed discontinued typed, discontinued type)
ICs for Cssette, Cssette Deck ANN, ANN Puse Detection s of Rdio Cssette, Cssette Deck Overview The ANN nd the ANN re the puse detection integrted circuits which select the progrm on the cssette tpe. In
More informationEngineering: Elec 3509 Electronics II Instructor: Prof. Calvin Plett,
Engineering: Elec 3509 Electronics II Instructor: Prof. Clvin Plett, emil cp@doe.crleton.c Objective: To study the principles, design nd nlysis of nlog electronic circuits. Description: In this course,
More informationAnalog computation of wavelet transform coefficients in real-time Moreira-Tamayo, O.; Pineda de Gyvez, J.
Anlog computtion of wvelet trnsform coefficients in rel-time Moreir-Tmyo, O.; Pined de Gyvez, J. Published in: IEEE Trnsctions on Circuits nd Systems. I, Fundmentl Theory nd Applictions DOI: 0.09/8.558443
More informationSynchronous Generator Line Synchronization
Synchronous Genertor Line Synchroniztion 1 Synchronous Genertor Line Synchroniztion Introduction One issue in power genertion is synchronous genertor strting. Typiclly, synchronous genertor is connected
More informationDesign and Modeling of Substrate Integrated Waveguide based Antenna to Study the Effect of Different Dielectric Materials
Design nd Modeling of Substrte Integrted Wveguide bsed Antenn to Study the Effect of Different Dielectric Mterils Jgmeet Kour 1, Gurpdm Singh 1, Sndeep Ary 2 1Deprtment of Electronics nd Communiction Engineering,
More informationArea-Time Efficient Digit-Serial-Serial Two s Complement Multiplier
Are-Time Efficient Digit-Seril-Seril Two s Complement Multiplier Essm Elsyed nd Htem M. El-Boghddi Computer Engineering Deprtment, Ciro University, Egypt Astrct - Multipliction is n importnt primitive
More informationResearch Letter Investigation of CMOS Varactors for High-GHz-Range Applications
Reserch Letters in Electronics Volume 29, Article ID 53589, 4 pges doi:1.1155/29/53589 Reserch Letter Investigtion of CMOS Vrctors for High-GHz-Rnge Applictions Ming Li, Rony E. Amy, Roert G. Hrrison,
More informationDesign and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram
INSTITUTE OFPHYSICS PUBLISHING Supercond. Sci. Technol. 16 (23) 1497 152 SUPERCONDUCTORSCIENCE AND TECHNOLOGY PII: S953-248(3)67111-3 Design nd implementtion of high-speed it-seril SFQ dder sed on the
More informationCHARACTERISTICS OF THE GPS SIGNAL SCINTILLATIONS DURING IONOSPHERIC IRREGULARITIES AND THEIR EFFECTS OVER THE GPS SYSTEM
CHRCTERISTICS OF THE GPS SIGNL SCINTILLTIONS DURING IONOSPHERIC IRREGULRITIES ND THEIR EFFECTS OVER THE GPS SYSTEM Eurico R. de Paula, I.J.Kantor, L.F.C. de Rezende ERONOMY DIVISION NTIONL INSTITUTE FOR
More informationThree-Phase NPC Inverter Using Three-Phase Coupled Inductor
ThreePhse NPC Inverter Using ThreePhse Coupled Inductor Romeu Husmnn 1, Rodrigo d Silv 2 nd Ivo Brbi 2 1 Deprtment of Electricl nd Telecommuniction Engineering, University of Blumenu FURB Blumenu SC Brzil,
More informationSoft switched DC-DC PWM Converters
Soft switched DC-DC PWM Converters Mr.M. Prthp Rju (), Dr. A. Jy Lkshmi () Abstrct This pper presents n upgrded soft switching technique- zero current trnsition (ZCT), which gives better turn off chrcteristics
More informationEngineer-to-Engineer Note
Engineer-to-Engineer Note EE-247 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our
More informationEE Controls Lab #2: Implementing State-Transition Logic on a PLC
Objective: EE 44 - Controls Lb #2: Implementing Stte-rnsition Logic on PLC ssuming tht speed is not of essence, PLC's cn be used to implement stte trnsition logic. he dvntge of using PLC over using hrdwre
More informationInformation-Coupled Turbo Codes for LTE Systems
Informtion-Coupled Turbo Codes for LTE Systems Lei Yng, Yixun Xie, Xiowei Wu, Jinhong Yun, Xingqing Cheng nd Lei Wn rxiv:709.06774v [cs.it] 20 Sep 207 Abstrct We propose new clss of informtion-coupled
More informationLecture 20. Intro to line integrals. Dan Nichols MATH 233, Spring 2018 University of Massachusetts.
Lecture 2 Intro to line integrls Dn Nichols nichols@mth.umss.edu MATH 233, Spring 218 University of Msschusetts April 12, 218 (2) onservtive vector fields We wnt to determine if F P (x, y), Q(x, y) is
More informationElectrically Large Zero-Phase-Shift Metamaterial-based Grid Array Antenna for UHF Near-Field RFID Readers
Electriclly Lrge Zero-Phse-Shift Metmteril-bsed Grid Arry Antenn for UHF Ner-Field RFID Reders Jin Shi, Xinming Qing, member IEEE, Zhi Ning Chen, Fellow, IEEE Abstrct A grid rry ntenn using zero-phse-shift
More informationInvestigation of Ground Frequency Characteristics
Journl of Electromgnetic Anlysis nd Applictions, 03, 5, 3-37 http://dx.doi.org/0.436/jem.03.58050 Published Online August 03 (http://www.scirp.org/journl/jem) Mohmed Nyel Electricl Engineering Deprtment,
More informationArc Furnace Modeling in ATP-EMTP
Arc Furnce Modeling in ATP-EMTP E. A. Cno Plt, Member, IEEE, nd H. E. Tcc, Member, IEEE Abstrct The use of the rc furnce nd its influence on the power system is being studied. A set of models tht llows
More informationTHE STUDY OF INFLUENCE CORE MATERIALS ON TECHNOLOGICAL PROPERTIES OF UNIVERSAL BENTONITE MOULDING MATERIALS. Matej BEZNÁK, Vladimír HANZEN, Ján VRABEC
THE STUDY OF INFLUENCE CORE MATERIALS ON TECHNOLOGICAL PROPERTIES OF UNIVERSAL BENTONITE MOULDING MATERIALS Mtej BEZNÁK, Vldimír HANZEN, Ján VRABEC Authors: Mtej Beznák, Assoc. Prof. PhD., Vldimír Hnzen,
More information5 I. T cu2. T use in modem computing systems, it is desirable to. A Comparison of Half-Bridge Resonant Converter Topologies
74 EEE TRANSACTONS ON POER ELECTRONCS, VOL. 3, NO. 2, APRL 988 A Comprison of Hlf-Bridge Resonnt Converter Topologies Abstrct-The hlf-bridge series-resonnt, prllel-resonnt, nd combintion series-prllel
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
Hll Ticket No Question Pper Code: AEC009 INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigl, Hyderd - 500 043 MODEL QUESTION PAPER Four Yer B.Tech V Semester End Exmintions, Novemer - 2018 Regultions:
More informationImplementation of Different Architectures of Forward 4x4 Integer DCT For H.264/AVC Encoder
Implementtion of Different Architectures of Forwrd 4x4 Integer DCT For H.64/AVC Encoder Bunji Antoinette Ringnyu, Ali Tngel, Emre Krulut 3 Koceli University, Institute of Science nd Technology, Koceli,
More informationSignal flowgraph concept First order integrator based filter Second order integrator based filter & biquads. Cascaded biquad sensitivity
EE47 Lecture 3 Lst week s summry Active Filters Active biquds Sllen Key & TowThoms Integrtor bsed filters Signl flowgrph concept First order integrtor bsed filter Second order integrtor bsed filter & biquds
More informationSection 16.3 Double Integrals over General Regions
Section 6.3 Double Integrls over Generl egions Not ever region is rectngle In the lst two sections we considered the problem of integrting function of two vribles over rectngle. This sitution however is
More informationJoanna Towler, Roading Engineer, Professional Services, NZTA National Office Dave Bates, Operations Manager, NZTA National Office
. TECHNICA MEMOANDM To Cc repred By Endorsed By NZTA Network Mngement Consultnts nd Contrctors NZTA egionl Opertions Mngers nd Are Mngers Dve Btes, Opertions Mnger, NZTA Ntionl Office Jonn Towler, oding
More information4110 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 66, NO. 5, MAY 2017
40 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 66, NO. 5, MAY 07 Trnsmit Power Control for DD-Underlid Cellulr Networs Bsed on Sttisticl Fetures Peng Sun, Kng G. Shin, Life Fellow, IEEE, Hilin Zhng,
More informationUniversity of North Carolina-Charlotte Department of Electrical and Computer Engineering ECGR 4143/5195 Electrical Machinery Fall 2009
Problem 1: Using DC Mchine University o North Crolin-Chrlotte Deprtment o Electricl nd Computer Engineering ECGR 4143/5195 Electricl Mchinery Fll 2009 Problem Set 4 Due: Thursdy October 8 Suggested Reding:
More informationExperimental Application of H Output-Feedback Controller on Two Links of SCARA Robot
INTERNATIONAL JOURNAL OF CONTROL, AUTOMATION AND SYSTEMS VOL.5 NO. Jnury 6 ISSN 65-877 (Print) ISSN 65-885 (Online) http://www.reserchpu.org/journl/jc/jc.html Experimentl Appliction of H Output-Feedck
More informationCSI-SF: Estimating Wireless Channel State Using CSI Sampling & Fusion
CSI-SF: Estimting Wireless Chnnel Stte Using CSI Smpling & Fusion Riccrdo Crepldi, Jeongkeun Lee, Rul Etkin, Sung-Ju Lee, Robin Krvets University of Illinois t Urbn-Chmpign Hewlett-Pckrd Lbortories Emil:{rcrepl,rhk}@illinoisedu,
More informationResearch on Applications of MOCVD based Automatic Control Circuits
Reserch on Applictions of MOCVD bsed Automtic Control Circuits YANG Yn-qing 1, SONG Xing 1 1 Tizhou Voctionl nd Technicl College Zhejing Tizhou 318, Chin Abstrct With the rpid development of semi-conductor
More informationTuning and Analysis of Fractional Order Controllers for Hard Disk Drive Servo System
Tuning nd Anlysis of Frctionl Order Controllers for Hrd Disk Drive Servo System Rkhi. S Dept. of Electricl nd Electronics Engineering Lourdes Mth College of Science nd Technology Thiruvnnthpurm, Indi Rohini
More informationSoft-decision Viterbi Decoding with Diversity Combining. T.Sakai, K.Kobayashi, S.Kubota, M.Morikura, S.Kato
Softdecision Viterbi Decoding with Diversity Combining T.Ski, K.Kobyshi, S.Kubot, M.Morikur, S.Kto NTT Rdio Communiction Systems Lbortories 2356 Tke, Yokosukshi, Kngw, 2383 Jpn ABSTRACT Diversity combining
More information& Y Connected resistors, Light emitting diode.
& Y Connected resistors, Light emitting diode. Experiment # 02 Ojectives: To get some hndson experience with the physicl instruments. To investigte the equivlent resistors, nd Y connected resistors, nd
More informationCharacterization of 3x3 and 4x4 multimode interference couplers in InP generic photonic integration technology
Chrcteriztion of x nd x multimode interference couplers in InP generic photonic integrtion technology Cittion for pulished version (APA): Pustkhod, D., Jing, X., vn Vliet, E. M., Willims, K. A., & Leijtens,
More informationKirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR):
SPH4UW Kirchhoff s ules Kirchhoff s oltge ule (K): Sum of voltge drops round loop is zero. Kirchhoff s Lws Kirchhoff s Current ule (KC): Current going in equls current coming out. Kirchhoff s ules etween
More informationEstimation of Disk Slip Position Error for Mobile Hard Disk Drives
Estimtion of Disk Slip Position Error for Mobile Hrd Disk Drives Peiqi Pn,, Yong Xio, Zhe Zheng,. College of Informtion Engineering Shenyng University of Chemicl Technology Shenyng, Lioning, 4, P.. Chin.
More informationTHE MODEL 682A05 BEARING FAULT DETECTOR (U.S. Patent No. 6,889,553) A New Approach for Predicting Catastrophic Machine Failure
TN4 THE MODEL 682A5 BEARING FAULT DETECTOR (U.S. Ptent No. 6,889,553) A New Approch for Predicting Ctstrophic Mchine Filure by Jmes Robinson Emerson Process Mngement Mitchell Illig IMI Sensors Thoms Brown
More information