Academic Course Description

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1 Academic Course Description SRM University Faculty of Engineering and Technology Department of Electronics and Communication Engineering VL2107 CMOS Mixed Signal Circuit Design Third Semester, (Odd semester) Course (catalog) description: As many real life applications involve both analog and digital circuits, this course aims to introduce the problems in implementing both in a single silicon wafer. Compulsory/Elective course: Elective for M. Tech (VLSI Design) - II year students Credit hours: 3 credits Course coordinator(s) Instructor(s) Dr. J. Selvakumar, Assistant Professor (S.G), Department of ECE Name of the Class Office Office instructor handling location phone M.Tech J. Selvakumar (VLSI TP10S5 Design) Relationship to other courses Selvakumar.j@ktr.srmuniv.ac.in Consultation Day 3 (1 3pm) Pre-requisites : VL2002, VL2004 Assumed knowledge : Knowledge on designing of analog and digital circuits References 1. Razavi, Design of analog CMOS integrated circuits, McGraw Hill, Edition Razavi, Principles of data conversion system design, Wiley IEEE Press, 1st Edition, Jacob Baker, CMOS Mixed-Signal circuit design, IEEE Press, Gregorian, Temes, Analog MOS Integrated Circuit for signal processing, John Wiley & Sons, Baker, Li, Boyce, CMOS: Circuit Design, layout and Simulation, PHI, Class schedule: Four 50 minutes Lecture sessions per week, for 15 weeks Section Schedule VLSI Design Day order 1 : Hr 3 Day order 2 : Hr 8 Page 1 of 5

2 Day order 5 : Hr 2 Professional component General - 0% Basic Sciences - 0% Engineering sciences & Technical arts - 0% Professional subject - 100% Broad area: Communication Signal Processing Electronics VLSI Embedded Test Schedule - Theory S. No. Test Portions Duration 1 Cycle Test Days 1 to 18 1 hr 40 min 2 Model Exam Days 1 to 45 3 hrs Course objectives Syllabus: To know mixed signal circuits like DAC, ADC, PLL etc. To gain knowledge on filter design in mixed signal mode. To acquire knowledge on design different architectures in mixed signal mode. VL2107- CMOS Mixed Signal Circuit Design Unit I - Phase Locked Loop (9 hours) Characterization of a comparator, basic CMOS comparator design, analog multiplier design, PLL - simple PLL, charge-pump PLL, applications of PLL. Unit II - Sampling Circuits (9 hours) Basic sampling circuits for analog signal sampling, performance metrics of sampling circuits, different types of sampling switches. Sample-and-Hold Architectures- Open-loop & closed-loop architectures, open-loop architecture with miller capacitance, multiplexed-input architectures, recycling architecture, switched capacitor architecture, current-mode architecture. Unit III- D/A Converter Architectures (9 hours) Input/output characteristics of an ideal D/A converter,, performance metrics of D/A converter, D/A converter in terms of voltage, current, and charge division or multiplication,, switching functions to generate an analog output corresponding to a digital input. Resistor-Ladder architectures, Current steering architectures Unit IV - A/D Converter Architectures (9 hours) Input/output characteristics and quantization error of an A/D converter, performance metrics of pipelined architectures, Successive approximation architectures, interleaved architectures. Unit V - Integrator Based Filters (9 hours) Low Pass filters, active RC integrators, MOSFET-C integrators, transconductance-c integrator, discrete time integrators. Filtering topologies - bilinear transfer function and biquadratic transferfunction. Page 2 of 5

3 Teaching Plan Day # Topics to be covered Reference 1. Characterization of a comparator Page No:691 Basic CMOS comparator. Problems on the 2. design of comparator Page No: Analog multiplier design (Multiplying quad) Page No: Analog multiplier design (Level shifting) Page No:710 Analog multiplier design (using squaring 5. circuit) - Problems Page No: Simple PLL (Blocks description) Page No: Simple PLL (Performance parameters) Page No: Charge pump PLL Page No:, Applications of PLL Reference book No.1, Chapter 15, Page No:572 Reference book No.5,Chapter 27, 10. sampling circuits, Basic sampling circuits Page No:756, Reference book No.1, Chapter 12, Page No:405 Performance metrics, Problems in the design Reference book No.1, Chapter 12, 11. of sampling circuits Page No: Types of sampling switches Reference book No.1, Chapter 12, Page No:410 Sample and hold architectures, Open loop 13. and closed loop architecture Page No: Open loop architecture with miller capacitance Page No: Multiplexed input architecture Page No: Recycling architecture 17. switched capacitor architecture current 18. mode architecture \ 19. I/P and O/P characteristics of an ideal A/D converter Page No: Performance metrics & Problems Page No:47 Page 3 of 5

4 21. D/A converter in terms of Voltage Page No: D/A converter in terms of Current Page No: D/A converter in terms of charge division or multiplication Page No: Switching functions Page No: D/A architectures - principle Page No: Resistor-Ladder architecture and problems Page No: Current steering architecture Page No: I/P and O/P characteristics of an ideal A/D converter Page No: Performance metrics & Problems Page No: Flash architecture & Problems Page No: Two step architecture 32. Interpolate architecture 33. folding architecture 34. Pipelined architecture 35. Successive approximation architecture 36. Interleaved architecture 37. Low pass filters & Problems 38. Active RC integrators & Problems 39. MOSFET-C integrator 40. Trans conductance integrator 41. Discrete integrator Page No:116 Page No:126 Page No:132 Page No:126 Page No:140 Page No:143 Reference book No.3,Chapter 35, Page No:393 Page No:395 Page No:404 Page No:407 Page No: Bilinear transfer function(active RC integrators, MOSFET-C integrator) Page No: Bilinear transfer function (Transconductance Page No:419 integrator, Discrete integrator) Biquadratic transfer function (Active RC integrators, Page No:422 Biquadratic transfer function (MOSFET-C integrator) Page No:423 Page 4 of 5

5 Evaluation methods Cycle Test - 20% Model Test - 20% Surprise Test - 5% Assignment / Term Paper - 5% Final exam - 50% Prepared by: J.Selvakumar, Assistant Professor(S.G), Department of ECE Dated: 24 June 2015 Revision No.: 00 Date of revision: NA Page 5 of 5

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