Introduction. Features. Applications. Ordering Information. Data Sheet PT7M7803/ / / µp Supervisor Circuits

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1 Features Precision supply-voltage monitor - 4.6V (PT7M7xxxL) - 4.8V (PT7M7xxxM) -.08V (PT7M7xxxT) -.9V (PT7M7xxxS) -.6V (PT7M7xxxR) -.V (PT7M7xxxZ) -.0V (PT7M7xxxY) 00ms reset pulse width Debounced CMOS-compatible manual-reset input (78, 78, 78, 78, ) Reset Output Signal for Watchdog and Power Abnormal, Manual Reset Reset Push-Pull output (PT7M7809,78,78, 784,78,74,74) Reset Open-Drain output (PT7M780/74) Voltage monitor for power-fail or low battery warning Guaranteed / valid at V CC =.0V Introduction The PT7M7xxx family microprocessor (µp) supervisory circuits are targeted to improve reliability and accuracy of power-supply circuitry in µp systems. These devices reduce the complexity and number of components required to monitor power-supply and battery functions. The main functions are:. Asserting reset output during power-up, powerdown and brownout conditions for µp system;. Detecting power failure or low-battery conditions with a.v threshold detector;. Watchdog functions; 4. Manual reset. Applications Power-supply circuitry in µp systems Ordering Information Part No. Push-Pull output Open-Drain output (push-pull) Manual Reset Input Power Fail Detector (.V) Watchdog Input PT7M780XT PT7M7809XT PT7M780XT PT7M78XT PT7M78XT PT7M78XT PT7M784XT PT7M78XT PT7M74XT PT7M74XT PT7M744XT PT7M74XT Package SOT- SOT- SOT-6 Suffix: X -- Monitored Voltage Suffix X L M T S R Z Y Reset threshold (V)

2 Contents Features... Ordering Information... Introduction... Block Diagram... Marking Information... 4 Pin Information... Pin Configuration... Pin Description... 6 Functional Description... 7 Reset Output... 7 Watchdog Timer... 7 Manual Reset... 7 Power-Fail Comparator... 7 Recommended Operation Condition... 8 Detailed Specifications... 8 Absolute Maximum Ratings... 8 DC Electrical Characteristics... 9 AC Electrical Characteristics... 0 Mechanical Information... Notes... 4

3 Block Diagram Figure. Block Diagram WDI Watchdog Transition Detector Vcc Watchdog Timer Timebase for Reset & Watchdog Vcc Reset Generator () V RST PFI PFO.V

4 Marking Information C ode Descriptio n 4 Part Number Yea r 4 Work Week Part Number Code Code Part No. Code Part No. Code Part No. AA PT7M7809L BC PT7M780L CE PT7M74L AB PT7M7809M BD PT7M780M CF PT7M74M AC PT7M7809T BE PT7M780T CG PT7M74T AD PT7M7809S BF PT7M780S CH PT7M74S AE PT7M7809R BG PT7M780R CI PT7M74R AF PT7M7809Z BH PT7M780Z CJ PT7M74Z AG PT7M7809Y BI PT7M780Y CK PT7M74Y AH PT7M780L BJ PT7M78L CL PT7M74L AI PT7M780M BK PT7M78M CM PT7M74M AJ PT7M780T BL PT7M78T CN PT7M74T AK PT7M780S BM PT7M78S CO PT7M74S AL PT7M780R BN PT7M78R CP PT7M74R AM PT7M780Z BO PT7M78Z CQ PT7M74Z AN PT7M780Y BP PT7M78Y CR PT7M74Y AO PT7M78L BQ PT7M784L CS PT7M744L AP PT7M78M BR PT7M784M CT PT7M744M AQ PT7M78T BS PT7M784T CU PT7M744T AR PT7M78S BT PT7M784S CV PT7M744S AS PT7M78R BU PT7M784R CW PT7M744R AT PT7M78Z BV PT7M784Z CX PT7M744Z AU PT7M78Y BW PT7M784Y CY PT7M744Y AV PT7M78L BX PT7M78L CZ PT7M74L AW PT7M78M BY PT7M78M DA PT7M74M AX PT7M78T BZ PT7M78T DB PT7M74T AY PT7M78S CA PT7M78S DC PT7M74S AZ PT7M78R CB PT7M78R DD PT7M74R BA PT7M78Z CC PT7M78Z DE PT7M74Z BB PT7M78Y CD PT7M78Y DF PT7M74Y 4

5 Pin Information Pin Configuration Figure. Pin Configuration SOT- PT7M780 PT7M7809 PT7M780 SOT- PT7M78 PT7M78 NC NC 4 4 PT7M78 PT7M784 PT7M78 WDI 4 WDI 4 4 SOT-6 PT7M74 PT7M74 PT7M744 PT7M PFI PFO 4 PFI PFO 4 PFI PFO 4

6 Pin Description Table. Pin Description P in Name Vcc PFI PFO WDI T yp e I Power Ground I O I Descriptio n M anual-reset: (CMOS). Active low. Pull low to force a reset. Reset remains asserted for the duration of the Reset Timeout Period after transitions from low to high. Leave unconnected or connected to if not used. P ower Supply: Reset is asserted when V remains asserted until V rises above V CC R Period (t once V rises above V ) RS CC G round Referenc e for all signals. R ST CC P ower-fail Voltage Monitor Input. When PFI < when not used. ST drops below the Reset Threshold Voltage ( V ). Reset RST and keep asserted for the duration of the Reset Timeout V PFT, PFO goes low. Connect PFI to or Vcc P ower-fail Output: it gets low and sinks current when PFI is less than.v; otherwise PFO stays high. Watchdog Input (CMOS). If WDI remains high or low for the duration of the watchdog timeout period ( t ), the internal watchdog timer trigger a reset output. Floating WDI or connecting WDI to a high- WD impedance three-state buffer disables the watchdog feature. The internal watchdog timer clears whenever reset is asserted or WDI occurs a rising or falling edge. O A ctive-low Reset Output (Push-Pull or Open-Drain). It goes low when Vcc is below the reset threshold. It remains low for about 00ms after one of the following occurs: Vcc rises above the reset threshold (V ), the watchdog triggers a reset, or goes from low to high. R ST O T he inverse of RES E T, active high. Whenever is high, is low. NC - No connectio n 6

7 Functional Description Reset Output A microprocessor s (µp s) reset input starts the µp in a known state. Whenever the µp is in an unknown state, it should be held in reset. The supervisory circuits assert reset during powerup and prevent code execution errors during power-down or brownout conditions. On power-up, once Vcc reaches about.0v, is a guaranteed logic low of 0.4V or less. As Vcc rises, stays low. When Vcc rises above the reset threshold, an internal timer releases after about 00ms. pulses low whenever Vcc drops below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the pulse continues for at least another 00ms. On powerdown, once Vcc falls below the reset threshold, stays low and is guaranteed to be 0.4V or less until Vcc drops below.0v. Fig 4 shows the timing relationship. The active-high output is simply the inverse of the output, and is guaranteed to be valid with Vcc down to.0v. Watchdog Timer The PT7M7xxx watchdog circuit monitors the µp s activity. If the µp does not toggle the watch-dog input (WDI) within.6s, reset asserts. As long as reset is asserted or the WDI input is toggled, the watchdog timer will stay clear and will not count. As soon as reset is released, the timer will start counting. WDI input pulses as short as 0ns can be detected. Disable the watchdog function by leaving WDI unconnected or by three-stating driver connected to WDI. Manual Reset The manual-reset input () allows reset to be triggered by a push button switch. has an internal pullup resistor, so it can be left open when not used. Power-Fail Comparator The power-fail comparator can be used for various purposes because its output and noninverting input are not internally connected. The inverting input is internally connected to a.v reference. Figure. Typical Application Circuit IN DC Linear Regulator µp Vcc Vcc µp Supervisory PFI Circuit WDI I/O Line PFO Interrupt 7

8 Detailed Specifications Absolute Maximum Ratings Storage Temperature o C to +0 o C Ambient Temperature with Power Applied o C to +8 o C Supply Voltage to Ground Potential (Vcc to ) V to +7.0V DC Input Voltage (All inputs except Vcc and ) V to V CC +0.V DC Output Current (All outputs)... 0mA Power Dissipation... 0mW (Depend on package) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operation Condition Table. DC Electrical Characteristics Sm ym D escriptio n T est Condition s Mn i Tp y p Mx a Uni t Supply Voltage for 7xxxL, 7xxxM V V CC Supply Voltage for 7xxxT, 7xxxS. 0.. V Supply Voltage for 7xxxR V Supply Voltage for 7xxxZ, 7xxxY. 4.. V V IH V IL T A Input High Voltag e 0.7VC C V Input Low Voltag e 0.VC C V Operating Temperatur e O C 8

9 DC Electrical Characteristics Table 4. DC Electrical Characteristics (Vcc=V RN +% to.v, T A = -40~8 C, unless otherwise noted) Symbol Description Test Conditions Min Typ Max Unit V CC Operating Voltage Range.0. V I CC Supply Current Vcc = V, No load 0 0 µa V IH Input High Voltage Pin:, WDI 0.7 Vcc V V IL Input Low Voltage Pin:, WDI 0. Vcc V V RST V RTH V OH V OL I LKG Reset Threshold Voltage (Note ) T A = -40 ~ 8 C Reset Threshold Hysteresis(Note ) Output High Voltage Output Low Voltage Open-Drain Output Leakage Current V RN-.% V RN V RN+.% PT7M7xxxL PT7M7xxxM PT7M7xxxT PT7M7xxxS PT7M7xxxR PT7M7xxxZ PT7M7xxxY.4.0. Vcc varies between V RN ±% 70 mv Vcc 4.V Isource=800µA Vcc-. Vcc.7V Isource=00µA 0.8 Vcc Vcc.8V Isource=0µA 0.8 Vcc Vcc 4.V Isink=.mA 0.4 Vcc.7V Isink=.mA 0. Vcc.V Isink=00µA 0. V CC > V TH(MAX) for PT7M780 and PT7M74 V V V µa V PFT PFI Input Threshold V PFI varies from.v and.0v.0..0 V I PFI I WDI PFI Input Leakage Current Average WDI Input WDI connected to V CC :.V 0 60 Current (Note ) WDI connected to -0 - ± na µa r pull-up resistor (internal) PT7M78/ PT7M78/784/78 7 PT7M74/74/ * Valid for both and. V RN is nominal reset threshold voltage. ** WDI is internally serviced within the watchdog period if WDI is left unconnected. kω 9

10 AC Electrical Characteristics Table. AC Electrical Characteristics Sm ym D escriptio n T est Condition s Mn i Tp y Mx a Unit s t RS Reset Pulse Width from low to High ms t WD Watchdog Timeout Period WDI and tied to V V + V CC > % R N, C C.. 6. s t Pulse Width µs t MD to Delay V CC =.0V 0 ns t WP WDI Pulse Width 0 ns Figure 4. Watchdog Timing Diagram V CC V RST V RST t RS t WD t RS t RS t WP t MD WDI t 0

11 Mechanical Information Figure. SOT BSC Datum A 0 o - 0 o BSC MAX SEATING PLANE X.XX Denotes Dimensions X.XX In Millimeters Notes: )Controlling dimensions in millimeters )Ref: EIAJ SC-74A )Foot length is measured at flat portion of foot, reference to Datum A

12 Figure 6. SOT BSC Datum A 0 o - 0 o BSC MAX SEATING PLANE X.XX Denotes Dimensions X.XX In Millimeters Notes: )Controlling dimensions in millimeters )Ref: EIAJ SC-74A )Foot length is measured at flat portion of foot, reference to Datum A

13 Figure 7. SOT BSC Datum A 0 o - 0 o BSC MAX SEATING PLANE X.XX Denotes Dimensions X.XX In Millimeters Notes: )Controlling dimensions in millimeters )Ref: EIAJ SC-74A )Foot length is measured at flat portion of foot, reference to Datum A

14 Notes Pericom Technology Inc. Web-Site: China: Asia Pacific: U.S.A.: No. 0 Building, /F, 48 Guiping Road, Shanghai, 00, China Tel: (86) Fax: (86) Unit 7, /F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (8) Fax: (8) Bering Drive, San Jose, California 9, USA Tel: () Fax: () Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. 4