The analysis and Compensation of dead-time effects in three phase PWM inverters

Transcription

1 The analysis and Compensation of dead-time effects in three phase PWM inverters Lazhar BEN-BRAHM Faculty of Technology University Of Qatar PO Box 273, Doha, Qatar Abstract The switching lag-time, which as MOSFET, GBT and others Therefore, the prevents the phase shortage of inverter arms, causes serious distortions of the output voltage understanding of the dead-time effect is crucial to the improvement of the performance of of the inverter This effect is well known as PWM inverters Furthermore, in some applidead-time eflect Several compensation methods were proposed to improve the output waveforms These proposed approaches did improve cations such as sensor-less vector control and direct vector control, the inverter output voltages are needed to calculate the rotor flux anthe inverter s output voltage waveforms The gle Unfortunately, it is very difficult to measure improved waveforms however still suffer from the zero-crossing phenomenon A new approach the output voltages and requires an additional hardware The most desirable method to obto overcome the zero current clamping in Voltage- tain the output voltage is to use the reference fed PWM inverters is proposed This paper describes the analysis of dead-time effect in three phases P WM inverters and the proposed scheme The conventional compensation methods as well voltage instead However, the relation between the output voltage and the reference voltage is nonlinear due to the dead-time effect [l] Thus unless the dead-time is properly compensated, as the zero crossing problem are highlighted The- the reference voltage can not be used instead oretical analysis and digital simulation were carried out to verify the analysis and the proposed scheme for dead time compensation of the output voltage Many approaches were proposed to overcome the effect of dead time [2],[3],[4],[5] These approaches do not treat the ntroduction PWM nverters are very well used in AC motor drives and UPS n inverters, time delay must be inserted in switching signals to prevent a short circuit in the dc link Although, this time delay guarantees safe operation of the inverter, it causes a serious distortion in the output voltages t results in a momentary loss of control, and the output voltage deviates from the reference voltage Since this is repeated for every switching operation, its effect may become significant This is known as the dead-time effect This effect is still apparent even with the recently developed fast switching devices such zero current clamping problem t is worth to note that the zero current crossing phenomenon is still not fully understood and not well resolved This zero crossing distortion is caused by the current ripples and the inadequate conventional compensation of the dead-time effect This paper presents a detailed analysis and method of compensations of the dead-time and the zero crossing phenomenon t proposes a new method to overcome the zero current crossing effect t is shown that the dead-time effect and the zero crossing compensation depend not only on the switching frequency but also on the load power factor and the load current Simulations are carried out using a simplified model of M drive system /98/$ EEE 792

2 2 Dead-time effect & Compensat ion 2 Effect iu,, iu put through diode D As a result, the output voltage is distorted as illustrated in Fig The direction of the load current flow, during the delay time, determines the output voltage rather than the control signals The voltage deviation due to the time delay opposes the current flow in either direction As a result, the deviation reduces the current magnitude, regardless of the current polarity However, if the current is around zero, the current may decrease to zero during the deadtime (Td) Whenever the current reaches zero during the deadtime and stays at zero level during the rest of the deadtime f this occurs, there is no means of controlling the output voltage As will be shown later, this phenomena zero crossing is difficult to avoid by the conventional techniques of compensation L yn Relation between voltage sign and output voltage J Figure : Deadtime effect in PWM inverters - A - 2A - 4rr - 5A r phase Fig shows the leg of one phase of the Figure 2: Deadtime effect PWM inverter, where power transistors are used as switching devices To turn off transistor X, The deviation voltage caused by the dead- U should be off and if the turn on speed is faster time is shown in Fig t is, as illustrated in than the turn of speed, a dc link short-circuit the Figure, a number of pulses with a constant will occur, therefore a delay time or dead-time amplitude equal to the dc link voltage Vd, a (generally with GBTs a delay in the order of constant pulse width equal to the delay time 20ps is inserted for safety) This dead-time is Td and a polarity opposed to the polarity of inserted by delaying the on signal of the tranthe load current and a frequency equal to the sistors by the delay time Td During this delay switching frequency of the inverter Although time, both transistors cease to conduct, and the this dead-time is very short, its accumulated eroutput terminal seems to be floating However, ror causes considerable distortions in the output due to the inductive load, the output current i is waveforms (see Fig 2) continuous, the current then flows through the freewheeling diodes D2 when the current is positive and the negative dc voltage is connected to the output f the current is negative, flowing toward the inverter, The positive voltage is out /98/$ EEE 793

3 \; \ ; &A&& * i ; : - 7r - 2 * 7 r T T r phase quency of the inverter pressed by the relation Therefore, np is ex- fc np = 7 where fc is the carrier or switching frequency and f is the operating frequency of the inverter The average deviation voltage height AV, caused by the cumulative of the deadtime pulses, is given by Figure 3: Deadtime Compensation 22 Compensation To analyse the distortion caused by the deadtime, we assume the followings: The turn-off time of the switching device is neglected 2 The switching frequency is bigger than the fundament a frequency 3 Current ripples are neglected Under the above assumptions, the dead-time effect can be analysed quantitatively These assumptions will facilitate the understanding of the compensation - techniques NVERTER AC/DC canverte Figure 4: Conventional compensation method The number of pulses, np, per period caused by the dead-time depends on the switching fre- Eq 2 shows that the deviation increases with the increase of the switching frequency fc Although Eq 2 shows that the dead-time distortion is independent of the inverter output frequency and voltage, it is worth to note that this distortion becomes significant at low speed when the inverter frequency f is low and the fundamental output voltage is also low This average deviation AV which is added to the reference voltage to calculate the new reference voltage applied to the inverter (see Fig 3): v: = v* +AV (3) This equation is used to derive the conventional compensation method shown in Fig 4 This approach is widely used in industrial PWM inverters to compensate for the dead-time effect t is based on Eq (3) and Fig 3 For simplicity, this concept uses the current reference to compensate for the dead-time effect The compensation signals in uvw-axis as well as dq-axis are shown in Fig 5 These signals were modified so that the inserted deadtime compensation voltages will keep the three phase output voltages of the PWM inverter balanced Note that d-current and the q-current compensation signals are different The current reference polarity is used instead of the actual current polarity This technique of compensation is valid under the assumption 3 However, in most practical case and especially for high power drive systems, the current has significant ripples and this will affect the compensation around the /98/$ EEE 794

4 Y ~ zero-crossing zone of the current The presence of significant ripples around zero-zone will lead to several zero-crossing of the actual current and with each zero-clamping the current polarity changes This makes the conventional compensation method umproper as it is using the reference current polarity to cancel the effect of the dead-time The conventional compensation described so far performs well when current ripples axe very small dead-time compensation The bandwidth of this smooth curve is defined as a function of current ripples f PWM inverter current ripples are large, then the "hysteresis" is large The curve inside is selected by cut and try error This method has improved the current distortion at the zero current clamping area in the voltagefed PWM inverter m j ) j j iu i, 0 i i j j j 2, ',* $ ~ - m Avu 0 ~ - :: Figure 6: Proposed method of compensation AV Y " -AV i i ; : 4 Simulations NVERTER Avw 0 : i i : eu e, e, n 3 i i i i i Figure 5: Conventional compensation signals Proposed method for dead-time & zero crossing effect compensat ion The proposed method is shown in 6 This Figure shows that the dead-time compensation is similar to the conventional method except for the zero-crossing; Close to the zero-zone we use a kind of "sniooth hysteresis" curve for the Figure 7: Simulation model Simulations were carried out to verify the proposed method 7 shows the scheme used for simulation, where the M is modeled as an R-L networks and a back-emf Fig 8 shows the simulation model results without dead-time compensation t is worth to note here the similarity between the distorted (d and 4) current waveforms in Fig 8 and Fig 5 Fig 9 depicted the current waveforms using the conventional compensation method n this Figure the zero-crossing phenomenon is apparent Fig 0 shows the proposed method for compensation of both the dead-time and the zero-crossing effects This shows that the proposed method /98/$ EEE 795

5 improves the current waveforms by eliminating the effect caused by the dead-time The current harmonics are greatly reduced as illustrated in Figure Fig -5 2 r tion Motor Drive system, ECON 98 (to be published), August 998 [a] Y Murai, T Watanabe and H wasaki Waveform distortion and correction circuit for PWM inverters with switching lagtimes, EEE, Trans on ndusty Applications, vol 23, No 5 pp , September/October 987 [3] T Sukegawa et all Fully digital vector controlled PWM VS-FED AC drives with an inverter dead-time compensation strategy, EEE, AS 88 Annual Meeting pp , 988 [4] SG Joeong and MH Park, The analysis and compensation of dead-time effects in PWM inverters, EEE, Trans on nd Electron, vol 38, No 2 pp 08-4, 99 [5] JW Choi and SK Sul nverter output voltage synthesis using novel dead-time compensation, EEE, Trans on Power Electronics, vol, No 2 pp , March 996 Figure 8: No compensation simulation 5 Conclusions 5 The PWM inverters dead time analysis and effect were analysed Conventional compensation methods as well as the zero crossing phenomena were highlighted A proposed method for deadtime and zero current clamping compensation was described in this paper The elimination of the zero current clamping effect in a voltage-fed PWM inverter was achieved Theoretical analysis and digital simulation were carried out to verify the analysis and the proposed scheme for dead time compensation The simulation has shown that the current waveforms output by the inverters were greatly improved References [l] L Ben-Brahim and S Tadakuma, Practical Considerations for Sensorless nduc j j q 4 -j j i ; j - Figure 9: Conventional compensation simulation /98/$ EEE 796

6 : : i : i : f a) n< / codpens&& / / ; "! /! j / / j j / / / :! i!! L () * : : : : : : : : : : : ~ " ~ / / / : / : / / *~?" : : : : : i : : : : ; : : : l - P - i i i * Figure 0: Proposed compensation simulation Figure : FFT analysis of current waveforms with (a) no deadtime compensation (b) conventional method (c) proposed method /98,'$ EEE 797