Pixelated Phase Mask as Novel Lithography RET

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1 Pixelated Phase Mask as Novel Lithography RET Yan Borodovsky a *, Wen-Hao Cheng b, Richard Schenker a, Vivek Singh a, a Intel Corporation, 52 NE Elam Young Parkway, Hillsboro, OR, USA 97124; b Formerly with Intel Mask Operations, Santa Clara, CA, Intel Corporation ABSTRACT Novel RET-Pixelated Phase Mask (PPM) is proposed as a novel Resolution Enhancement Technique (RET). PPM is made of pixels of various phases with lateral dimensions significantly smaller than the illuminating radiation wavelength. Such PPM with a singular choice of pixel dimensions acts as a mask with variable phase and transmission due to radiation scattering and attenuation on pixel features with the effective intensity and phase modulated by the pixel layout. Key properties of the pixelated phase masks, the steps for their practical realization, and the benefits to random logic products discussed. Wafer patterning performance and comparative functional yield results obtained for a 65nm node microprocessor patterned with PPM, as well as current PPM limitations are also presented. Keywords: phase shift mask, PSM, thick mask, ILT, computational lithography, variable phase & transmission PSM 1. INTRODUCTION In Lithography Novel is not often equal to Useful and even less so to Necessary yet without exception it spells Painful to those who have to take it through development into manufacturing. So it is important to state upfront the reasons we embarked on development of Novel RET and to comment on benefits and challenges of its use. As intergenerational resolving power of imaging systems has lagged behind Moore s Law scaling demand, progressively more aggressive off-axis illumination complimented by the use of phase shifted masks have had to be used to support patterning at progressively lower Raleigh s k 1 conditions. The use of ever more aggressive off-axis illumination solutions, that made possible supporting inter-generational linear scaling for minimal pitch 1D features, also resulted in progressively forbidding such scaling of 2D features, as well as features with intermediate pitches required for traditional logic area density scaling with single exposure patterning. To resolve this density scaling conflict at ever lower k 1 progressively more restrictive design rules are employed, resulting in ever escalating complexity and cost of OPC, DFM and time needed for mask making development and manufacturing. To counteract this trend one had to deal with one or more of Novel s be it exploration of limits of Computational Lithography to extend 193nm based dry lithography as far as possible with existing tooling and materials, deal with layout split, overlay challenges and additional costs of double patterning with dry 193nm, or to address defectivity and overlay challenges of at that time emerging Immersion 193nm Lithography. Intel did address all of above but subject of this paper is just one: Novel RET that takes advantage of Intel s own computational lithography and mask making expertise to provide single exposure patterning solutions for unrestricted design rules logic layouts down to pitches with k 1 = PIXELATED PHASE MASK SINGLE PHASE ETCH MASK WITH VARIABLE PHASE AND TRANSMISSION Consider imaging by projection optics of pure phase edge glass mask with grating having half pitch equal X as on the figure shown here. Fig. 1 shows the computed transmission at the image (wafer) plane, glass Fig. 2 show the relative phase in the near field of the mask shown for 193nm projection system with NA=.85, partial coherence σ =.3(conventional) and Mag=.25 using x Thick mask rigorous EM solver as well as Thin Mask solver for grating pitches 18 down to imaging system cutoff. Near Field (NF) relative phase on Fig. 2 is defined as air * yan.borodovsky@intel.com; phone (53) ; fax: φ relative _ phz = ENF( glass_18) ENF ( glass_ ) Optical Microlithography XXI, edited by Harry J. Levinson, Mircea V. Dusa, Proc. of SPIE Vol. 6924, 6924E, (28) X/8/$18 doi: / Proc. of SPIE Vol E-1

2 Transmission Grating (Thick Mask) Grating (Thin Mask) /2 pitch on mask (nm) Relative Phase (degree) Thin Mask Grating 1/2 pitch on mask (nm) Grating TM Grating TE Figure 1. Transmission to image plane from the phase Figure 2. Relative phase (near field) of the phase grating (5/5 duty cycle) above modeled system cutoff grating (5% duty cycle). Red line system cutoff The un-shaded area above system cutoff is lithography traditional domain. Masks features having pitch below system cutoff are traditionally of no interest to lithography as it is common understanding that no spatial information from such features will be transferred to image plane by imaging optics. Yet if one explore properties of projection optics imaging with masks having such features using rigorous EM Modeling one would find (Fig. 3 and 4) that at pitches on a mask significantly below imaging optics cutoff projection system regains its ability to transmit to the image plane radiation illuminating such phase mask as well as phase information dependent on fine dimensional structure of such features. Transmission Grating (Thick Mask) Grating (Thin Mask) /2 pitch on mask (nm) Relative Phase (degree) Grating 1/2 pitch on mask (nm) Grating TM Grating TE Figure 3. Transmission to the image plane from the phase grating (5/5 duty cycle) for modeled projection system Effective Phase(degree) Figure 5 3% glass, TM 3% glass, TE 5% glass, TM 5% glass, TE 7% glass, TM 7% glass, TE Grating 1/2 pitch on mask(nm) Figure 4. Relative phase (near field) of the phase grating (5/5 duty cycle) Further exploration of this phenomena show that such information coding by features with pitches much below cutoff indeed can be quite efficient and flexible. Figure 5 show the near field s effective phase for grating structure, when grating duty ratio differs from 5/5. Effective phase φ eff is computed for complex transmission t from t (, ) = ENF x y dxdy φ = t eff Proc. of SPIE Vol E-2

3 Transmission Grating (Thick Mask) Checkerboard /2 pitch on mask (nm) Effective Phase(degree) Checkerboard /2 pitch on mask [nm] glass grating, TM glass grating, TE Figure 6. Transmission to the image plane from the phase Figure 7. Effective phase (near field) of the phase grating (5/5 duty cycle) and glass checkerboard glass grating and checkerboard Figures 6 and 7 show far field transmission and near field effective phase for glass gratings as well as a glass checkerboard mask shown for same projection imaging system and mask dimensions as in the cases considered above Glass grating (top-down view) Glass checkerboard (top-down view) glass 18 glass Figure 8 provided pictorial representation of the physical phenomena responsible for the observed transmission and phase behavior shown on Figures 3 through 7 for a mask having 5/5 grating structure. Our understanding of the observed phenomena follows: Phase edge mask, with pitches below the imaging system cutoff continue to resolve incoming electric field as shown on Figure 8, but very little radiation gets transmitted to the far field as it gets scattered into diffractive orders with angles exceeding the projection system s entrance pupil NA. Yet as the phase edge pitch decreases further the projection system regains its ability to transmit oncoming radiation to the image plane when the phase mask features pitch becomes so small as compared to the incoming radiation wavelength that it cannot sufficiently resolve oncoming EM field, and in effect just averages it without scattering in diffracted orders. This is fundamentally a thick mask effect that cannot be observed in a framework of Kirchhoff approximation. The strong dependence of radiation intensity and phase transmitted by projection system to image plane on individual feature shapes and geometric layouts formed by ensembles of such features for the mask EM field averaging pitch region led us to conclude that the afore mentioned general projection imaging system responses can provide a novel means of information transfer enhancement by using features on the mask with pitches resulting in field averaging by the mask. At the same time mask features with pitches in a range between projection system cutoff and mask induced field averaging can be used to encode and transfer image information corresponding to larger opaque portions of layout if 2-tone glass mask will be used to form the desired pattern on a wafer. It is apparent from the data shown on a Figs. 3-8 that such a mask, in spite of having a singular phase etch depth, will exhibit properties of a mask with variable effective phase and transmission as coded by the layout of field averaging features (pixels). It became our intent to explore the possible use of the additional information content transfer provided by such mask to provide extended scalability for 2D Proc. of SPIE Vol E-3

4 layout features, as well as process window enhancements for 1D pitches, that otherwise fall into forbidden gaps with aggressive off-axis illumination employed for low k 1 patterning and as a result construct methodology, tooling and mask making and processes capable of supporting unrestricted logic layouts with production worthy process window and throughput at lowest possible resolution for 1D and 2D layout features. x glass 18 x glass 18 x glass 18 air air air Phase(degree) x(nm) Phase(degree) x(nm) Phase(degree) x(nm) Below Mask Cutoff Above Mask Cutoff Above Mask Cutoff Below Imaging Optics Cutoff Below Imaging Optics Cutoff Above Imaging Optics Cutoff Mask near field averaging Mask resolved near field Mask resolved near field Projection system transmit Insignificant transmission to Projection system transmit diffracted order light to image plane image plane from phase grating orders to image plane Mask Information 2 Tone Chromeless Mask Mask Information Transfer Enhancement Enabling Transfer Phase (degree) Relative Phase TM Relative Phase TE Effecitve Phase TM Effective Phase TE Transmission /2 pitch on mask (nm) Transmission Figure 8. Pixelated Phase Mask - Depiction of principle and usage for enhanced information transfer. Proc. of SPIE Vol E-4

5 3. PIXELATED PHASE MASK KEY DECISIONS A number of critical decisions had to be made to provide practical solutions to construct such a mask. Those are, but not limited to: Type of mask to use (2 tone, 3 tone, 4 tone, glass only, glass + absorber, etc), Pixel lateral dimensions consistent with variable phase and transmission mask information coding and transfer requirements, as well as existing and planned mask making write, inspect and repair capabilities, Pixel etch depth consistent with above, Near Field Computational Lithography Tool and Methodology capable of computing the full field mask near field with accuracy, cost and throughput consistent with wafer patterning specifications and mask tapeout requirements, including final mask database imaging validation. Inverse Lithography Tool and Methodology capable to derive full field mask pixelation resulting in desired intensity distribution at the wafer plane that reproduce design layout intent with accuracy, fidelity and process window consistent with specifications as well as productivity and cost necessary for high volume manufacturing requirements including final mask database validation, Mask Process and Tools capable of resolving all pixel arrangements on a full field mask capable of reproducing design layout intent on a wafer with fidelity and process window as well as productivity and cost necessary for high volume manufacturing, Choice for Technology Demonstration Vehicle. 4. CONSIDERATIONS AND RESULTS 4.1 Mask Most of the choices we made were dictated by practical considerations imposed by the schedule of the technology targeted for possible initial PPM RET use (45nm node), the perceived complexity of mask making, the complexity, accuracy and productivity of tooling needed to provide the computational lithography solutions as well as the estimated rate of learning and resources expected, and eventually committed, in support of such effort Mask Type. While we considered several different types of mask substrates, we chose alternating phase shifted mask technology as it was known to produce the highest possible image contrast with partially coherent illumination as well as being a technology with which we were very familiar after many years of development Also, while preliminary analysis showed a benefit of higher contrast with the use of traditional 3-tone AltPSM mask [1] we decided to limit the PPM mask stack to 2 tone (a glass with no absorber) based on our assessment of the inability, at the time, of both existing and near term planned mask making equipment to support dimensional control for sub-12nm pixels through 2 consecutive critical layer e-beam alignments and 2 critical chrome and glass etches, consistent with the modeling assumptions requirements Choice of pixel shape and size was similarly dictated more by practical considerations than by exhaustive analysis. Given the enormous and,at the time, yet to be comprehended complexity involved in finding the best arrangement between over a trillion pixels on a mask to produce the desired image on the wafer we decided on the simplest possible approach one shape/one size. Deciding on the dimensions of the pixel was less arbitrary: laterally, its upper bound was dictated by its field averaging effectiveness to support the desired variable phase and transmission nature for such a mask. Consequently for 193nm exposure tool with NA of.85 it had to be smaller than roughly 12nm on a mask as can be seen from Fig 3-8. The lower bound on pixel lateral size was decided upon considering the expected write time for a full field mask with various pixels sizes <12nm and the projected minimal features size that Intel mask making would be able to develop and support the within required dimensional tolerances on a full field mask by the completion time of the project objectives demonstration. As a result, 1nm lateral pixel size on a mask (at 4X) was chosen as a compromise between considerations stated above. For pixels with 1nm side dimensions the accuracy of our proprietary EM modeling approximation that we had at the time, while sufficient up to the etch depth corresponding to and somewhat exceeding 18 o phase shift for standard AltPSM masks, degraded as much as 25% for pixels with etch depth significantly above that (See [2] for more details). This and the great benefit of using processing and metrology already in place in support of traditional AltPSM mask making at Intel led us to adopt an etch depth for phase shifted pixels to be the traditional nm. The benefit of considerations stated above outweigh, in our opinion, the possible contrast degradation from the ideal due to effective phase shift for such pixels in the near field to be different from 18 when field averaged by and together with neighboring pixels. Proc. of SPIE Vol E-5

6 4.1.3 Mask Processing. While the mask processing front end required significant incremental effort and enhancement in order to be able to support patterning of pixelated masks with the needed dimensions and corresponding tolerances [3], and a tapeout processes capable of accounting and compensating for mask processing non-linearities existing at the time needed to be developed [1], the lack of established back end modules such as non-distractive 1nm pixel phase depth metrology, uncertainty in the usefulness of existing tools for patterned pixelated phase mask defect inspection and the absence of qualified tools and methodology to identify and repair individual pixels or their ensemble presented significant technology gap that had to be closed in order to make pixelated phase mask a reality. Solutions to field averaging pixel metrology were provided through the combination of nanotube equipped AFM, scatterometry and SEM, while inspection capabilities were based on scanning of the aerial image produced by the PPM under illumination conditions identical to those to be employed by patterning on the wafer scanner were developed - with adequate sensitivity and capture rate for defects normally observed on pixelated phase mask. Its correlation to a defects printability (Figure 9) allowed for efficient capture and disposition of defects based on such inspection methodology as well as providing an expedient means for pixelated phase mask specific defect reduction learning and troubleshooting. This and the use of high resolution electron beam mask repair allowed for efficient repair of both types of pixels as well as ensembles of several of them as describes in [3] thus facilitating the complete development cycle for defect free pixelated phase masks with 1nm pixel size. Figure 9. Upper left shows contours generated from Aerial Image mask inspection tool comparing reference die to die with mask defect before repair. White areas indicate regions where defect region produces extra wafer features (resist trenches) and black areas indicate regions where defect region produces a smaller resist trench. Center right shows aerial inspection results after e-beam repair. Upper right image shows top-down CD-SEM image of defective area on mask before repair. In that region, a glass mesa has collapsed. Bottom left and right images show resist pattern on wafer pre and post repair respectively. An other example of inspection and repair of PPM mask defect resulting is printable side lobe is shown on Figure 1 with Inspection s off-focus aerial image on a left and printed results on a right r U S LIIIIIIIIjrs Before repairs F= Best Focus(BF) F=BF+.15 F= BF+.25 Proc. of SPIE Vol E-6

7 I o.i. Zoom I 5. nm Section 3 I 2 I 1! I : Height 5. urn mu Database of relevant portion of the mask AFM showing defect in phase area Best Focus (BF) BF+.15 BF+.25 Figure 1. Before and after Sidelobe defect inspection and repairs (bottom figure after PPM repair) 4.2 Pixelated Phase Mask Near Field Accuracy and Productivity In order to derive a useful mask arrangement of the sub-wavelength dimension pixels, an approximation to rigorous Maxwell solution that is both accurate and fast enough to support iterative computation of pixelated mask near field within practical time limits. As described in a separate paper by two of the authors [2], none of the existing fast methods for modeling thick mask efforts was accurate enough to model our pixelated masks. Consequently, we enhanced one of the methods, the domain decomposition method, to take into account scattering effects arising from 1) the fact that the pixels, at mask dimension, are about half the size of the wavelength, 2) the rounding of the corners of the pixels, and 3) the sloping sidewall of the etched topography. The resulting models captured the contours within a few nanometers of the rigorous simulation, and post-calibration, matched the silicon very well, as seen in Figure Computational Lithography Performance and Productivity The details of the computational methods that were used to obtain the pixelated mask designs are described in reference [2]. The key elements of this method are the fast thick mask model described above, an optimization algorithm that finds the near optimal configuration of pixels out of the enormously large number of possible combinations, an objective function that helps drive the optimization, the ability to remove pixel configurations that present a problem in the mask making process, and machinery to handle full chip tapeout. The computation involved is very large in spite of several breakthroughs to increase speed, although massive parallelization enables the viability of full chip tapeout. Proc. of SPIE Vol E-7

8 Figure 11. Contours predicted by PPM modeling and actual patterning in resist 4.4 Process window enhancements with pixelated phase masks. The computational lithography approach described and employed to find pixels arrangements on the pixelated phase mask, present ill posed mathematical problem with its solution characterized by high degree of degeneracy, thus many possible.pixels arrangements might be found that lead to solutions satisfying predetermined optimization constrains. Without describing in details the cost function employed, it is sufficient to state that the main emphasis was on satisfying the required CD control for all 1D and 2D features present in the design layout through focus and exposure range to the degree necessary to support the targeted process technology generation in high volume manufacturing DOF and Process Latitude Enhancements The use of Pixelated Phase Masks allowed for significant DOF improvement for multitude of 2D features and showed the necessary improvement in DOF for 1D features with pitches traditionally having unacceptably low DOF with traditional patterning involving aggressive off axis illumination associated with k1 patterning below <.37, thus eliminating the need for forbidden gaps in the corresponding DR solution space for 1D features. Figure 12 show the DOF for various 1D pitches at k1=.29 (193/.93 and 8nm pixels), Figure 12 show various 2D features performance vs DOF at k1=.35 (with 1nm pixels) Figure 14 shows the 2D MEEF improvement achievable with PPM over 6%EPSM at k1= nm Defocus Best Focus +75nm Defocus Figure nm min pitch patterning thru focus using PPM with 193nm,.8 in out cquad Illumination,.93NA (k1=.29). Pixel size on mask is 8nm (4X). Usable depth of focus ~ 1nm (defects clearly seen at +75nm defocus) Proc. of SPIE Vol E-8

9 -1nm Defocus Best Focus +1nm Defocus - oo rr 11!1Oll. ooooooa Figure nm min pitch patterning thru focus using PPM with 193nm, annular illumination and.85na (k 1 =.35). Pixel size on mask is 1nm (4X). EPSM MEEF ~12.5 ( PPM MEEF ~7.5 k Figure 14. Comparison of simulated 2D MEEF performance of PPM vs 6% EPSM for trench ends of 6nm (min 1D pitch of 12nm). Simulations use a calibrated resist model, 193nm, λ=.93na, c-quad illumination (k1=.29). PPM pixel size=8nm (4X). Contours are +/-4 and nm/edge (4x) sizing. EPSM MEEF is > 5% higher than PPM. Proc. of SPIE Vol E-9

10 4.4.2 Weak Images, MEEF and Side lobes Detection and Correction Sensitivity to mask making tolerances is usually characterized by MEEF values associated with the chosen patterning and mask making solutions for both 1D and 2D features, as computed for masks with post OPC treatment applied. MEEF is a preeminent parameter impacting the choice and production worthiness of patterning solutions selected to support given manufacturing node. Yet no conventional OPC is used to alter locations of the pixels edges on Pixelated Phase Mask as only phase and phase shifted pixels of singular constant dimensions were used for the synthesis of 2 tone PPM mask. Thus the assessment of sensitivity of PPM to mask making tolerances is performed by introducing mask making errors within the agreed upon mask making tolerances to the optimized PPM database directly with the corresponding assessment of the quantitative impact of such errors to image quality. Sensitivity to global and local lateral pixel dimensions as well as phase shifted pixel phase errors must be established to ensure consistency of the specified PPM mask making tolerances with the required range of dimensional control for patterned features. Special care must be taken to ensure that the modeling environment for such analysis is capable of reproducing the studied mask making imperfection in all 3 dimensions accurately as well as to insure correct and sufficiently accurate derivation of the corresponding near field terms for such altered pixel geometries with the efficiency necessary to address a full field mask database. In the course of such studies we learned that the imaging response to referred PPM mask imperfection is rich, non-intuitive and in most cases hard to characterize by worst case MEEF concepts and terminology normally applied to traditional mask making and patterning as we were not able to identify such category as worst case for any of the PPM masks produced. The results on Figure 15 illustrate the need for dense checking as PPM expected pattern contour deviation from target can vary dramatically over short distances. Figure 15. Unacceptably large CD change over very short distance resulting from database stitching error for pattern at k1=.29 ( green pixel having wrong phase assignment) It is worth noting that, while capable of improving process performance for a multitude of 1D and 2D features at low k 1, 2-tone PPM generally produces images with moderate image contrast. As a result one has to be vigilant in devising and using means of weak image detection and local image improvement as well as printable side lobe spotting (Figure 17) and suppression as an integral part of pixelated phase mask synthesis. And while some weak images are formed by combinations of pixels that allow analysis and comprehension of the reasons why such pixels combinations will in most cases lead to weak image formation (Figures 15 and 16) others, such as shown on Figure 18, are not. Figure 16. Pixelation solution resulting in accept unacceptably weak image On-target Low-dose High-dose -.15µm focus +.15µm focus Proc. of SPIE Vol E-1

11 45'un from top of resist (31.SisU) X-A,do I Figure 17. Mask making Tolerance study showing sidelobe printability down to 45nm below resist surface for 12nm per side pixels CD mask error a) b) c) On-target Low-dose High-dose -.15µm focus +.15µm focus Figure 18. Weak image detectable through modeling (a) resulting in patterning defect (b) that is not easily attributed to particular pixels arrangement on a mask (c) [ mask image flipped around vertical axis] As a result pre-tapeout validation for a PPM mask must include full mask image investigation through the expected range of mask making tolerances and the expected wafer processing conditions to ensure usability of the PPM mask with the derived arrangement of pixels. Dense checking routines needed to be employed to ensure quality of the imaging solutions for a given PPM mask synthesis prior to mask final tapeout, as contour deviation from the desired might occur along exceedingly short contour distances. Proc. of SPIE Vol E-11

12 4.5 Technology Demonstration Cedar Mill CPU Cedar Mill that was Intel s leading CPU in production (65nm node) at the demonstration time was chosen as PPM technology demonstration vehicle. All of the described above learning was applied to synthesis and tapeout of a Cedar Mill CPU Metal 1 Pixelated Phase Masks. Two defect free pixelated phase masks were manufactured and split lot patterned as a technology demonstration with product yield as the key demonstration parameter. While we are not at liberty to disclose actual number of yielding dies for the control and PPM demonstration splits, it is sufficient to say that product patterned with pixelated phase mask yielded a number of fully functional Cedar Mill CPUs on multiple 3mm wafers within close proximity to that of the control group manufactured through mature 65nm node production. See [1] for more details on this topic Pixelated Phase Mask Use and Extendibility The focus of the work presented here is to describe novel RET technique capable of supporting continuous area density scaling with an emphasis on layers having complex line/space layouts such as multi-core CPU s metallization layers that needed to be patterned at lowest possible k 1 with no or the least possible amount of design rule restrictions. It must be noted that while a pixelated phase mask can be used in principal on any layer, there are some factors that limits its use, extendibility and scalability for future applications Edge scalloping While the line edge variation ( scalloping ) observed in the resist patterned by pixelated phase mask show remarkably low ratio to that of the dimensions of individual pixel on a mask ( CD wafer /Pixel size mask <1:5 or after its demagnification by 4:1 projection system (<1:12) for a pixel with 8 nm on a side, [1] some layers such as gate might not being able to accommodate this additional source of line width variance Mask repair In order to extend the benefits of using field averaging features with use of pixelated phase masks to future technology nodes pixels with progressively smaller lateral dimensions on a mask must be used. While we were able to extend mask making technology capabilities to produce pixelated phase masks with pixels lateral dimensions of 8nm that were inspectable and repairable within 1% of required CD Control on the wafer (with 3D sizing) using same technology solutions for a pixelated phase mask down to 56 nm pixel lateral dimensions on the mask in support of 22nm node logic patterning with 193nm immersion tools presented challenge that might be not possible to overcome with existing mask material and mask making processing. A key issue is absence of effective repairs for damaged o pixels with lateral dimension less then 1/3 of either the radiation wavelength or its etch depth that can restore mask imaging characteristics across process window as shown on Fig. 19 and 2. A change of mask substrate to a high refractive index material or use of different mask stack needs to be investigated for its feasibility to support a sub-6nm pixelated phase mask. Image CD: um 8nm qz collapse mask repair Focus : um Region to repair- missing 1x3 mesa CD thru focus for different repair sizes/depths, Desired Figure 19. 1X3 (8nm pixel) mesa damaged (left), effective repairs to restore it performance found with lateral and vertical dimension change (3D sizing) found % CD -1% CD ref_sim def_sim nm-x 1nm-Y 344nm (2π)-Z 8nm-X 1nm-Y 292nm (1.7π)-Z Proc. of SPIE Vol E-12

13 8nmbias_2pi ref_sim -1% 1% 8nmbias1.7pi8nmx 1nmbias1.7pi8nmx Deep etch region to repair missing 1x4 mesa CD thru focus for different repair sizes/depths, Desired Figure 2. 1X4 (56nm pixel) mesa damaged (left), no effective repairs to restore it performance with any combination of lateral and vertical dimension change (3D sizing) found Pixelated Phase Mask and ILT A Pixelated Phase Mask exhibits properties of a mask with variable phase and transmission thus it is uniquely suitable to support advancements in Inverse Lithography due to its ability to provide the highest number of quantization terms needed to reduce general ILT solutions to practice [4,5]. Yet it is remains to be seen if it will find significant use in the manufacturing environment as both ILT and PPM technologies are complex, relatively immature and might be at the limits of their usefulness in support of single exposure patterning for 22nm node for logic products. Its extension to double patterning is possible [5,6] yet its use there is not assured either due to its relative complexity as compared to many other methods suggested in support of the pitch division to be used in support of future IC manufacturing with 193nm exposure tools. 5. CONCLUSION Novel RET Pixelated Phase Mask (Figure 21) was developed to support patterning of complex logic layout with unconstrained design rules at k1=.29 and above. In addition to the traditionally used mask features with dimensions above projection system cutoff, pixelated phase mask utilize features (pixels) with pitch well below illumination wavelength resulting in averaged by mask and transmitted to projection optic s image plane EM field with transmission and effective phase dependent on spatial arrangement of such features. The use of mask field averaging features allowed for patterning solutions with improved performance for 2D and 1D logic design features. EM field averaging by mask features is fundamentally thick mask effect observed for mask features with dimensions below incoming radiation wavelength that require accurate and efficient Computational Lithography tools for its use in development and production environment. Combination of Pixelated Phase Masks and Inverse Computational Lithography has potential to provide solutions to ultimate area density scaling for both single and double exposure patterning solutions available with optical lithography yet its use and proliferation might be hindered by complexity involved in many critical steps involving synthesis and manufacturing for such mask. 6. ACKNOWLEDGEMENTS Authors would like to thank many current and former Intel employees who helped us reduce what was pretty wild idea at the time to reality in a timeframe of single technology node Pathfinding and Development. We would like to acknowledge Chiang Yang, Jeff Farnsworth, Ken Buckmann, Karmen Yung, Wai Kwok, Andrew Jamison, Yi-Ping Liu, Brian Irvine, Jun Kim, Eric Frendberg, Malahat Tavassoli, Nathan Wilcox and Rajesh Nagpal of Intel Mask Operation for their contribution and support, Hocheol Shin for help with some Figures, Paul Davids, Srinivas Bollepalli and everyone who worked on modeling and computational aspects of this project at Intel s Design Technology Solutions as well as Edita Tejnil, Peng Liu, Matt Vernon, Erdem Ultanir and David Hwang for contributions, insights and support provided to this effort at the time they were our colleagues at Intel. Proc. of SPIE Vol E-13

14 U Figure 21. AFM of Pixelated Phase Mask used for Technology Validation/Cedar Mill CPU REFERENCES [1] Schenker, Richard et al., Integration of Pixelated Phase Masks for full chip random logic layers, Proc. SPIE Vol. 6924, 28 [2] Singh, Vivek et al., Making a trillion pixels dance, Proc. SPIE Vol. 6924, 28 [3] [4] Farnsworth, Jeff et al., Fabrication of defect free full-field pixelated phase mask, Proc. SPIE Vol. 6924, 28 Davids, Paul et al., Generalized inverse problem for partially coherent projection Lithography Proc. SPIE Vol. 6924, 28 [5] Poonawala, Amyn et al., A pixel-based quantization approach to inverse lithography, Microelectronic Engineering, Volume 84, Issue 12, December 27, Pages [6] Poonawala, Amyn et al., ILT for double exposure lithography with conventional and novel materials Proc. SPIE Vol. 652, 27 Proc. of SPIE Vol E-14

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