Large Area Interposer Lithography
|
|
- Cornelia Wiggins
- 6 years ago
- Views:
Transcription
1 Large Area Interposer Lithography Warren Flack, Robert Hsieh, Gareth Kenyon, Manish Ranjan Ultratech, Inc 3050 Zanker Road, San Jose. CA John Slabbekoorn, Andy Miller, Eric Beyne IMEC Kapeldreef 75 B-3001 Leuven, Belgium Medhat Toukhy, PingHung Lu, Yi Cao, Chunwei Chen AZ Electronic Materials USA Corp. 70 Meister Ave, Somerville, NJ USA Abstract Large area silicon or glass interposers may exceed the maximum imaging field of step and repeat lithography tools. This paper discusses the lithographic process used to create a large area interposer on a stepper by the combination of multiple subfield exposures. Overlay metrology structures are used to confirm the relative placement of the subfields to construct the interposer. Routing lines from 1.5 to 4.0 µm in width are evaluated to measure critical dimension (CD) control where the lines cross the subfield boundaries. CD metrology at the bottom and top of the photoresist is performed using a top down CD-SEM. Finally large area test interposers are patterned using two subfields on a 1X stepper and processed through a Cu electroplating module for detailed characterization. The CD control of routing lines as they cross the subfield boundary can be optimized by using a shaped or tapered line end design. Lithography simulation using Prolith modeling software by KLA-Tencor is matched to experimental results and then used to evaluate performance of various line end designs. Larger latitude for overlap error was observed for the tapered line end compared to the standard square line end. The experimental and modeled results in this study show the capability of using stepper lithography to produce large area interposers with 1.5 µm I/O routing line dimensions. Introduction Over the last few decades, IC technology has used shrinking gate dimensions to increase gate switching speed and decreased operating voltage to reduce power consumption. As the demand for improved form factor and superior battery life accelerates, the semiconductor manufacturing supply chain is taking a closer look at back end of line (BEOL) manufacturing technology. Innovative IC packaging solutions are being developed to meet the needs in consumer electronics. Furthermore, IC packaging now is widely seen as a method to prolong Moore s law [1]. Many companies are evaluating the use of silicon interposers with through silicon vias (TSV) to address requirements for higher performance and smaller form factor packages. Interposer technology is less complex than full 3D stacking and therefore offers an advantage in time to market. It is currently viewed as the next major step in cost effective advanced packaging technology. Key advantages of silicon interposers include high routing line density, excellent electrical and thermal performance, lower power requirements than equivalent single-chip packages through combination of multiple chips on one substrate, and the possibility of integrating passives into the substrate [2,3]. The individual device die can provide numerous functions including memory, logic, analog and MEMS (micro-electromechanical systems). Achieving high bandwidth between individual die on the interposer requires fine pitch routing lines. For advanced wide I/O applications, it is anticipated that interconnect line widths of less than 2 µm will be needed. A step and repeat (stepper) lithography system provides the necessary patterning capability for high resolution devices with zero printable defects. However, for some designs the interposer area can exceed the maximum stepper field size. Large Interposer Fabrication The requirement for patterning large area devices with stepper lithography is not new. Superchips from the VHSIC (Very High Speed Integrated Circuit) program were constructed using macrocells [4]. Each macrocell was a selfcontained integrated circuit placed in a single stepper field and only interconnect layout rules were used at crossing field boundaries [5, 6]. A more recent demand for large area devices is for infrared focal plane arrays used for aerospace applications [7]. The image sensor pixels are contained within a stepper field and only interconnect routing is allowed to cross stepper field boundaries similar to superchips. Since interposers are designed to interconnect single chip devices, the field stitching considerations are similar to focal plane arrays and superchips. A large area interposer can be fabricated by splitting the interposer design into multiple sections where each section is smaller than the maximum field size of the step-and-repeat lithography system. Figure 1 shows a 50 by 50 mm interposer split into a top half (purple) and a bottom half (pink). This two subfield approach would work for a lithography system with a field size greater than 50 by 25 mm.
2 Figure 1. The large area interposer design is split into top and bottom halves for stepper lithography layout. A reticle for the lithography system is then fabricated for each section of the interposer. Figure 2 shows the layout for a 1x reticle that supports placing multiple fields on one plate. Here the top half of the interposer (purple) is field 1 on the reticle and the bottom half of the interposer (pink) is field 2 on the reticle. Figure 2. 1X reticle layout for an interposer split into two fields. The reticle size is 150 by 150mm. This reticle can then be used on the lithography stepper to image the full interposer on the wafer by alternating the patterning of rows of field 1 (purple) and field 2 (pink) as shown in figure 3. The interposer routing lines that cross the boundary of the top half and bottom half of the interposer are stitched by allowing a small amount of Y overlap between the two fields. The same approach could be used to fabricate even larger area interposers by having additional reticle fields stitched in both the X and Y direction. This paper evaluates using this field stitching process to meet the requirements for advanced silicon interposer manufacturing. Experimental Methods Exposures are performed on an Ultratech AP300 advanced packaging stepper with a 0.16 NA Wynne-Dyson lens [8]. This catadioptric optical system design permits the use of broadband illumination from a mercury arc lamp, and the system used in this study has a capability to select i-line, ghline or ghi-line wavelengths. The tool is equipped with a WEE (Wafer Edge Exposure) unit for exposing the edge of the wafer and a WEP (Wafer Edge Protection) unit for protecting a predefined outer edge of the wafer. The WEE enables precise removal of photoresist from the wafer edge creating an electrical contact that is required for electroplating. The WEP blocks exposure light and can be used to retain photoresist on a thin ring inside the WEE creating a protective seal ring to prevent leakage of solution during the electroplating step. The large area interposer evaluated for this study is 44.0 by 44.0 mm with interconnect lines covering the whole chip area. Since the exposure field of the 1X stepper used in this study is 44x26.7mm, the interposer design is split in two fields each with a size of 44 by 22mm similar to figures 1 and 2. The reticle set was designed to include test structures that provide evaluation of overlay and CD performance at the field boundaries. For this case only a Y stitch is required. Multiple test structures were created to evaluate reticle field stitching performance. Figure 4 shows a line integrity structure with six sets of line and space patterns with varying CD and pitch. The patterns above the red stitch line are on reticle field one and the patterns below the red stitch line are on reticle field two. The CD of the test structures vary from 1.5 µm line and space on the left side to as large as 4.0 µm line and 2.0 µm space on the right. The 0.5 in blue above the pattern indicates that the top and bottom half have a stitch overlap in Y of +0.5 µm between the fields. Additional line integrity structures were created with field stitch overlaps varying from as small as -0.5 µm to as large as µm. Figure mm wafer layout with 21 interposers. The interposer size for this case is 50 by 50 mm. Figure 4. CD performance features with varying pitches. The red line indicates the stitch between field 1 and field 2. The 0.5 above the structure indicates the Y overlap in microns. An electrical test structure was also created to evaluate the field stitch performance of electroplated Cu lines. Figure 5 shows a serpentine/comb four point probe structure. The pattern above the red stitch line is on reticle field one and the pattern below the red stitch line is on reticle field two. The test structures range from 1.5 µm line and space to 3.0 µm line and space. The field overlap in Y was +0.5 µm. Initial test of the interposer stitching was performed on bare silicon wafers using JSR IX845 positive tone photo resist. The resultant photoresist structures are evaluated for overlay performance and CD behavior at the stitching
3 boundary and are used as the reference for the simulation modeling discussed in the Simulation of Field Stitching section of this paper. Figure 5. Serpentine/Comb structure. The red line indicates the stitch between field 1 and field 2. Next the lithographic process was evaluated on Cu seed 200mm wafers using actual device process conditions. The Cu interconnect lines are fabricated using a semi-additive electroplating technique as shown in figure 6. In this technique a Cu seed layer consisting of 30 nm TiW and 50 nm of Cu is deposited on the wafer which acts as the current distributing layer during the electroplating process (figure 6.1). Next a 3.5 µm thick positive photoresist is coated on the wafer and the area to be electroplated is opened to the Cu seed via the lithography process (figure 6.2). The resist is descummed and then 2.5 µm of Cu is electroplated on the wafer (figure 6.3). The photoresist is then stripped off of the wafer (figure 6.4). The Cu seed is wet etched followed by wet etch of the TiW to create the final structure (figure 6.5). over a wide range of film thickness. Therefore, chemically amplified (CA) resist platforms are believed to be more suitable than (DNQ) platform to fulfill the future needs for advanced packaging applications such as interposers. The higher photospeed of CA resist reduces exposure times and considerably improves the cost of ownership of the lithography tool. This study employed AZ EXP CN-3 positive resist, which is based on a phenolic polymer, CA platform. This resist can produce vertical sidewalls with minimal footing on Cu substrates, and is capable of resolving submicron patterns in 3.5µm thick resist using i-line lithography. The exposure latitude of 1.5 µm lines and spaces measured on a 0.16 NA stepper was 18% with a ±10% CD criterion. Processing conditions for AZ EXP CN-3 are summarized in table 1. All resist processing was performed on a TEL ACT12 Clean Track which is equipped with high viscosity pumps for thick resist processing. CD metrology was performed on a KLA 8250XR CD-SEM. Process Step Conditions Soft Bake 120 seconds at 110 C Post Exposure Bake 60 seconds at 90 C Development 30 seconds x 2 (double puddle) in 0.26N TMAH developer with surfactant Table 1. Process conditions used for AZ EXP CN-3 resist. The 1X stepper offers multiple alignment options, and for this study both blindstep and zero layer alignment were evaluated. Blindstep uses the XY stage encoder along with a previously calibrated transform to accurately print a multiple field array. The zero layer technique requires a dedicated array of field alignment targets to be printed on the wafer. These targets are used to align and stitch two adjacent reticle fields together to optimize overlay. Overlay metrology was performed using microscope measurements and using the selfmetrology feature on the 1X stepper. Results For this study the AZ EXP CN-3 resist was exposed at i- line using a nominal exposure dose of 140 mj/cm 2. The resist was optimized to produce a 1.5 µm line and space pitch on Cu seed wafers. A cross section of 3.5 µm thick AZ EXP CN3 photoresist is shown in figure 7(a). The resist exhibits an excellent profile with minimal footing. Cross sections of Cu plated lines are shown in figure 7(b). Figure 6. Wafer Process Flow to fabricate Cu interconnect lines using of a semi-additive electroplating technique. The novolak/diazonaphthoquinone (DNQ) positive tone resist platform is approaching its process limits to adequately meet the demands of advanced packaging applications. DNQ high absorption and low sensitivity impose significant limitations on its resolution, pattern profiles, and photospeed Figure 7. (a) Cross section of 3.5 µm thick AZ EXP CN3 photoresist. The exposure dose is 140 mj/cm 2 and the focus
4 offset is 0 µm. (b) Cross section of Cu plated metal lines before Cu seed etch. Both cases are for line and space pattern with 3 µm pitch. Sample interposer structures were stitched together using two lithography fields. The resist line at the stitch area was evaluated for three different Y axial offsets (overlap). Figure 8(a) shows a positive overlap of 1.0 µm and the positive resist line at the stitch decreases in CD. Figure 8(c) shows a negative overlap of 0.5 µm and the resist line bulges out and merges with adjacent lines. Note that these images are taken before the descum step which would further open the spaces between resist lines. lines across a field boundary. In this case the lateral offset was set at 0.25 µm. Figure 10. Stitched plated metal lines at 3 µm pitch with (a) no lateral offset and (b) a lateral offset of 0.5 µm. The overlap is 0.5 µm. The red line is the field stitch location. Figure 8. Effect of Y overlap at the stitch of resist spaces for a 3 µm pitch structure. The resist feature is dark in these images. The lateral offset is 0.25 µm. These images are taken before the resist descum process. The effect of the Y overlap was also evaluated after Cu electroplating. Figure 9 shows three cases: (a) 1.0 µm overlap, (b) 0.5 µm overlap, (c) -0.5 µm overlap (a gap). A large overlap creates a bulge in the line at the stitch whereas a gap creates a line constriction. Taken to the extreme, a large overlap can create an electrical short and a large gap can create and electrical open. Therefore to preserve line integrity the Y overlap error must be controlled. Based on these experimental results a 0.5 µm overlap is used in the rest of this study. Figure 11. Electroplated metal lines at stitch with (a) 4 µm line and 2 µm space and (b) 4 µm and 3 µm pitches equal line and space pitches. Both cases have a lateral offset of 0.25 µm. The steps following resist development also influence the shape and size of the Cu lines. Both descum and the seed removal steps need to be optimized for effective control of CD. Descum is essential for uniform plating results because it reduces the surface tension of the photoresist to allow proper wetting to the Cu seed. However, this process consumes photoresist and the CD of the resist opening increases as a result. Figure 11(a) shows one line exhibiting some nonuniformity which indicates that the descum is on the limit of being too soft. Figure 9. Effect of Y axial offset at the stitch for plated metal lines for a 3 µm pitch structure. Figure 10(a) shows a top down SEM of stitched dense plated lines with 3 µm pitch. The plated lines form within the spaces of the resist pattern. This view shows an optimized stitch for which the actual stitch location is difficult to discern. A red horizontal line is added to the stitch location. For instructive purposes it is useful to include moderate amounts of lateral offset in the stitch in order to clearly denote its position. Figure 10(b) shows stitched plated line with a large lateral offset of 0.5 µm. With large lateral offset the line is well defined and maintains adequate width, however the spaces between the lines become constricted. Tilted SEM images of the plated lines are shown in figure 11(a) and 11(b). The images illustrate ability to fabricate line/space metal lines down to the 1.5 µm and to stitch these Figure 12. Top down view of Cu plated metal lines (a) before Cu seed etch and (b) after seed etch. Both cases are for 3 µm pitch, line and space pattern. The seed etch also can have a large impact on the shape and size of the Cu lines. During wet etching of the Cu seed, the electroplated structures are also etched with a reduction of
5 CD as a result as shown in Figure 12. To reduce this effect the Cu seed thickness needs to be as thin as possible in order to minimize the etching time. For example, using a standard Cu seed thickness of 150nm results in more than 400 nm CD loss, which would be unacceptable for creating 1.5 µm Cu lines. This is the reason that a 50nm Cu seed was used in this study. Figure 13 shows top down view of a Cu electroplated serpentine/comb structure with a 3µm pitch. Visual inspection reveals no line breaks or shorts in any of the serpentine/comb structures. Future work includes electrical characterization of these four point probe structures. Figure 13. Cu electroplated serpentine/comb structure with a 3 µm pitch. Visual inspection reveals no line breaks or shorts in the structure. Simulation of Field Stitching A lithography simulation program (Prolith version from KLA-Tencor) was used to study the effect of stitching overlap and lateral offset on the resist pattern for stitched vertical lines. The pattern consists of 1.5 µm dense vertical lines. Two photomask passes are used to accurately simulate the separate top and bottom field exposures. Figure 14 illustrates the construction of the Prolith model for a standard square corner line end. Figure 15. Simulation conditions for stitching line with 45 degree tapered ends with lateral offset and overlap. Experimental test patterns were exposed in 2.7 µm thick JSR IX845 resist on a 200 mm wafer, and SEM photos were taken to document resist performance at the stitch for different offsets. Figure 16(a) shows top down SEM of a stitch with measured X and Y offset of 0.2 and 0.75 µm respectively. The corresponding figure 16(b) shows a Prolith 3-dimensional resist simulation of the same conditions. Note the resist feature is grey in this figure. Experimental and simulated results show very good agreement, which gives confidence in using modeling to investigate the effect of stitching overlap and lateral offset on line quality. Figure µm stitched lines with lateral offset of 0.2 µm and overlap of 0.75 µm. (a) Top down SEM of resist pattern. (b) Prolith simulation of the resist pattern with square ends. To minimize the CD variation across the stitch a reasonable starting goal is to hold the lateral offset to 20% of the line width. For 1.5 µm line/space this translates into a ±0.3 µm offset range. A similar number can be used for the overlap range. Prolith simulation was used to determine the effectiveness of these criteria for stitched lines. Figure 14. Simulation conditions for stitching line with square ends with lateral offset and overlap. The top and bottom exposures are independently simulated. The construction of a tapered line end is shown in figure 15. The objective is to determine whether changing the shape of the line ends from square ends can improve process margin for misalignment. For the square line ends the zero overlap condition is defined where the two line ends just meet. For the tapered line ends the zero overlap is defined where the full width shoulders of the tapers meet. In both cases, a positive overlap moves the bottom feature up in Y relative to the top feature. For lateral offset a positive shift moves the bottom feature to the right in X relative to the top feature. Figure 17. Square end stitch simulation of 1.5 µm lines with overlaps varying from 0.2 µm to 0.8 µm and lateral offsets of 0.0 (top row) and 0.3 µm (bottom row).
6 Figure 17 shows a sequence of simulations for different values of overlap and lateral offset for square line ends. Overlap range shown in figure 17 is 0.2 to 0.8 µm. Note that resist feature is grey in this figure. CD at the stitch is well controlled, however one can see that as overlap decreases, the resist line starts to bulge at the stitch; and with increasing overlap, the resist line constricts. The effect of a lateral offset of 0.3 µm is shown in the bottom row. For large lateral offsets the rotation of the dense lines at the stitch reduces the spacing between adjacent lines. Both overlap and lateral offset need to be controlled in order to maintain line integrity across the stitch. However the overlap parameter has the larger effect on CD at the stitch. The effect of tapering the line ends was studied using simulation. A 45 degree taper ending in a point was investigated. For this end shape, the definition of zero overlap is where the full width bases of the tapered lines meet. Prolith simulations show a range of overlap from -0.5 to 0.1 µm where linewidth is moderately well controlled as shown in figure 18. The effect of a lateral offset of 0.3 µm is shown in the bottom row. The stitched lines with tapered line ends have smoother transitions than the stitched lines with square line ends. The resist linewidth at the simulated stitch was measured for various overlaps, with zero lateral offset as shown in figure 19. For both square and tapered line end types the CD versus overlap behavior can be well described by a quadratic fit. For comparison between square and tapered line ends the overlap is shifted such that zero overlap corresponds to the condition where the CD at the stitch equals the nominal linewidth of 1.5 µm. The nominal CD is obtained at an overlap of 0.41 µm for the square ends and µm for the tapered ends. It is apparent that the slope of the tapered end curve is less than the square end curve, indicating larger latitude for overlap error for the tapered end. If a ±10% CD tolerance is allowed the overlap range is 25% larger for the tapered line end relative to the square line end. The resist model based on JSR IX845 resist characteristics can be compared to actual measured CD data using AZ EXP CN-3 resist. Note that these measurements are of the space between resist lines, since the space defines the size of the plated lines. Figure 20 shows the 1.5 µm resist features on a 3.0 µm pitch with 0.3 µm and 0.8 µm overlap. Here the total overlap is calculated by adding the design overlap and the measured registration at the stitch site. The CD at the stitching line is measured and compared to the nominal CD just above and below the stitching line. At 0.3 µm overlap the CD of the space is 342 nm smaller than nominal and at 0.8 µm the CD of the space is 256 nm larger than nominal. The estimated optimum CD at the stitch occurs at 0.59 µm overlap based on linear interpolation, or 0.55 µm based on fitting to the curvature in figure 19 for square end lines. The experimental data for AZ EXP CN-3 resist shows a reasonably good fit to the model. Further experiments would be needed to fine tune the model specifically for AZ EXP CN-3 resist. Figure 18. Tapered ends stitch simulation of 1.5 µm lines with overlaps varying from -0.5 µm to +0.1 µm and lateral offsets of 0.0 (top row) and 0.3 µm (bottom row). Figure 19. Comparison of resist line CD versus overlap for square and tapered line ends. Data from Prolith modeling of JSR IX845 resist. Overlap scale is shifted so that zero overlap corresponds to the condition where CD at the stitch equals the nominal linewidth of 1.5 µm. Figure 20. AZ EXP CN-3 resist lines (dark features) at stitch. 1.5 µm CD lines and spaces across the stitching line for +0.3 and+0.8 µm overlap. Lateral offset is 0.1 µm. Conclusions Extending device performance increasingly relies on advancements in back end technologies such as the use of very large interposer designs with aggressive interconnect density requirements. A stepper system provides the necessary patterning capability for high resolution devices with zero printable defects. However to produce large area interposers requires stitching of stepper subfields. This study experimentally investigated patterning copper lines with lateral dimensions as small as 1.5 µm line/space in a vertically stitched 44 by 44 mm device. To achieve this an experimental AZ EXP CN-3 resist was employed. The resist must meet a combination of requirements for this application
7 including high resolution, steep sidewalls and chemical resistance to the Cu electroplating process. Lithography simulation was used to further study the line fidelity across the subfield boundary, including the effect of stitching error and effect of changing the line end shape at the stitch. Larger latitude for overlap error was observed for the tapered line end compared to the standard square line end. This characterization is useful for improving process control of the lithography step. This work demonstrates that stitching of subfields for interposer interconnects can be achieved by leveraging existing stepper lithography and processes technologies. Acknowledgments We would like to thank Patrick Jaenen and Inge de Preter of IMEC for the cross-sectional SEM images. We would also like to thank Geraldine Jamieson, Sofie Robert, Joris Tuinstra and Sander van Gompel of IMEC for their help setting up the wafer processes. References 1. Flemming, J., et al.; Cost Effective 3D Glass Microfabrication for Advanced Electronic Packages, 2013 IPC APEX Conference & Exhibition, San Diego, California, February Vardaman, J. et. al., TechSearch International: Developments in 2.5D: The Role of Silicon Interposers, August Hogan, M., Silicon interposers: building blocks for 3D- ICs, Solid State Technology, June, Stroll, Z. VHSIC Submicron technology at TRW, GOMAC Digest, Flack, W. et. al., Lithographic Manufacturing Techniques for Wafer Scale Integration, International Conference on Wafer Scale Integration, San Francisco, Flores, G. et. al., Lithography Strategies for Wafer Scale Integration, KTI Microlithography Seminar Proceedings, San Diego, Rogalski, A., Semiconductor Detectors and Focal Plane Arrays for Far-Infrared Imaging, Opto-Electronics Review, 21(4) Flores, G. et. al, Lithographic Performance of a New Generation i-line Optical System, Optical/Laser Lithography VI Proceedings, SPIE 1927 (1993).
MICROBUMP LITHOGRAPHY FOR 3D STACKING APPLICATIONS
MICROBUMP LITHOGRAPHY FOR 3D STACKING APPLICATIONS Patrick Jaenen, John Slabbekoorn, Andy Miller IMEC Kapeldreef 75 B-3001 Leuven, Belgium millera@imec.be Warren W. Flack, Manish Ranjan, Gareth Kenyon,
More information450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D
450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D Doug Anberg VP, Technical Marketing Ultratech SOKUDO Lithography Breakfast Forum July 10, 2013 Agenda Next Generation Technology
More informationCharacterization of a Thick Copper Pillar Bump Process
Characterization of a Thick Copper Pillar Bump Process Warren W. Flack, Ha-Ai Nguyen Ultratech, Inc. San Jose, CA 95126 Elliott Capsuto, Craig McEwen Shin-Etsu MicroSi, Inc. Phoenix, AZ 85044 Abstract
More informationMarket and technology trends in advanced packaging
Close Market and technology trends in advanced packaging Executive OVERVIEW Recent advances in device miniaturization trends have placed stringent requirements for all aspects of product manufacturing.
More informationReducing Proximity Effects in Optical Lithography
INTERFACE '96 This paper was published in the proceedings of the Olin Microlithography Seminar, Interface '96, pp. 325-336. It is made available as an electronic reprint with permission of Olin Microelectronic
More informationCopyright 1997 by the Society of Photo-Optical Instrumentation Engineers.
Copyright 1997 by the Society of Photo-Optical Instrumentation Engineers. This paper was published in the proceedings of Microlithographic Techniques in IC Fabrication, SPIE Vol. 3183, pp. 14-27. It is
More information1X Broadband Wafer Stepper for Bump and Wafer Level Chip Scale Packaging (CSP) Applications
1X Broadband Wafer Stepper for Bump and Wafer Level Chip Scale Packaging (CSP) Applications Doug Anberg, Mitch Eguchi, Takahiro Momobayashi Ultratech Stepper, Inc. San Jose, California Takeshi Wakabayashi,
More informationLithographic Performance of a New Generation i-line Optical System: A Comparative Analysis. Abstract
Lithographic Performance of a New Generation i-line Optical System: A Comparative Analysis Gary Flores, Warren Flack, Lynn Dwyer Ultratech Stepper 3230 Scott Blvd. Santa Clara CA 95054 Abstract A new generation
More informationPhotolithography I ( Part 1 )
1 Photolithography I ( Part 1 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science
More informationProcess Optimization
Process Optimization Process Flow for non-critical layer optimization START Find the swing curve for the desired resist thickness. Determine the resist thickness (spin speed) from the swing curve and find
More informationDOE Project: Resist Characterization
DOE Project: Resist Characterization GOAL To achieve high resolution and adequate throughput, a photoresist must possess relatively high contrast and sensitivity to exposing radiation. The objective of
More information(Ar [ Si O Si O] m )n
The widespread adoption of advanced packaging techniques is primarily driven by electrical device performance and chip form factor considerations. Flip chip packaging is currently growing at a 27% compound
More informationMajor Fabrication Steps in MOS Process Flow
Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide Silicon substrate Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment
More informationoptical and photoresist effects
Focus effects in submicron optical lithography, optical and photoresist effects Chris A. Mack and Patricia M. Kaufman Department of Defense Fort Meade, Maryland 20755 Abstract This paper gives a review
More informationMeRck. nlof 2000 Series. technical datasheet. Negative Tone Photoresists for Single Layer Lift-Off APPLICATION TYPICAL PROCESS
MeRck technical datasheet AZ Negative Tone Photoresists for Single Layer Lift-Off APPLICATION AZ i-line photoresists are engineered to simplify the historically complex image reversal and multilayer lift-off
More informationThe End of Thresholds: Subwavelength Optical Linewidth Measurement Using the Flux-Area Technique
The End of Thresholds: Subwavelength Optical Linewidth Measurement Using the Flux-Area Technique Peter Fiekowsky Automated Visual Inspection, Los Altos, California ABSTRACT The patented Flux-Area technique
More informationOptolith 2D Lithography Simulator
2D Lithography Simulator Advanced 2D Optical Lithography Simulator 4/13/05 Introduction is a powerful non-planar 2D lithography simulator that models all aspects of modern deep sub-micron lithography It
More informationMeRck. AZ nlof technical datasheet. Negative Tone Photoresist for Single Layer Lift-Off APPLICATION TYPICAL PROCESS. SPIN CURVE (150MM Silicon)
MeRck technical datasheet AZ nlof 5510 Negative Tone Photoresist for Single Layer Lift-Off APPLICATION AZ nlof 5510 i-line photoresist is engineered to simplify the historically complex image reversal
More informationMicrolens formation using heavily dyed photoresist in a single step
Microlens formation using heavily dyed photoresist in a single step Chris Cox, Curtis Planje, Nick Brakensiek, Zhimin Zhu, Jonathan Mayo Brewer Science, Inc., 2401 Brewer Drive, Rolla, MO 65401, USA ABSTRACT
More informationMICROCHIP MANUFACTURING by S. Wolf
MICROCHIP MANUFACTURING by S. Wolf Chapter 19 LITHOGRAPHY II: IMAGE-FORMATION and OPTICAL HARDWARE 2004 by LATTICE PRESS CHAPTER 19 - CONTENTS Preliminaries: Wave- Motion & The Behavior of Light Resolution
More informationTutor43.doc; Version 8/15/03 T h e L i t h o g r a p h y E x p e r t (November 2003)
Tutor43.doc; Version /15/03 T h e L i t h o g r a p h y E x p e r t (November 2003) Scattering Bars Chris A. Mack, KLA-Tencor, FINLE Division, Austin, Texas Resolution enhancement technologies refer to
More informationDemo Pattern and Performance Test
Raith GmbH Hauert 18 Technologiepark D-44227 Dortmund Phone: +49(0)231/97 50 00-0 Fax: +49(0)231/97 50 00-5 Email: postmaster@raith.de Internet: www.raith.com Demo Pattern and Performance Test For Raith
More informationPart 5-1: Lithography
Part 5-1: Lithography Yao-Joe Yang 1 Pattern Transfer (Patterning) Types of lithography systems: Optical X-ray electron beam writer (non-traditional, no masks) Two-dimensional pattern transfer: limited
More informationKey Photolithographic Outputs
Exposure latitude Depth of Focus Exposure latitude Vs DOF plot Linearity and MEEF Isolated-Dense Bias NILS Contrast Swing Curve Reflectivity Curve 1 Exposure latitude:the range of exposure energies (usually
More informationCopyright 2002 by the Society of Photo-Optical Instrumentation Engineers.
Copyright 22 by the Society of Photo-Optical Instrumentation Engineers. This paper was published in the proceedings of Optical Microlithography XV, SPIE Vol. 4691, pp. 98-16. It is made available as an
More information450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum July 10, 2013 Doug Shelton Canon USA Inc.
450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum 2013 July 10, 2013 Doug Shelton Canon USA Inc. Introduction Half Pitch [nm] 2013 2014 2015 2016 2017 2018
More informationLithographic Process Evaluation by CD-SEM
Lithographic Process Evaluation by CD-SEM Jason L. Burkholder Microelectronic Engineering Rochester Institute of Technology Rochester, NY 14623 Abstract-- In lithography employed in IC fabrication, focus
More informationHolistic View of Lithography for Double Patterning. Skip Miller ASML
Holistic View of Lithography for Double Patterning Skip Miller ASML Outline Lithography Requirements ASML Holistic Lithography Solutions Conclusions Slide 2 Shrink Continues Lithography keeps adding value
More informationRadial Coupling Method for Orthogonal Concentration within Planar Micro-Optic Solar Collectors
Radial Coupling Method for Orthogonal Concentration within Planar Micro-Optic Solar Collectors Jason H. Karp, Eric J. Tremblay and Joseph E. Ford Photonics Systems Integration Lab University of California
More informationFeature-level Compensation & Control
Feature-level Compensation & Control 2 Sensors and Control Nathan Cheung, Kameshwar Poolla, Costas Spanos Workshop 11/19/2003 3 Metrology, Control, and Integration Nathan Cheung, UCB SOI Wafers Multi wavelength
More informationCopyright 2000, Society of Photo-Optical Instrumentation Engineers This paper was published in Optical Microlithography XIII, Volume 4000 and is made
Copyright 00, Society of Photo-Optical Instrumentation Engineers This paper was published in Optical Microlithography XIII, Volume 4000 and is made available as an electronic reprint with permission of
More informationEffect of Reticle CD Uniformity on Wafer CD Uniformity in the Presence of Scattering Bar Optical Proximity Correction
Effect of Reticle CD Uniformity on Wafer CD Uniformity in the Presence of Scattering Bar Optical Proximity Correction Konstantinos Adam*, Robert Socha**, Mircea Dusa**, and Andrew Neureuther* *University
More informationOPC Rectification of Random Space Patterns in 193nm Lithography
OPC Rectification of Random Space Patterns in 193nm Lithography Mosong Cheng, Andrew Neureuther, Keeho Kim*, Mark Ma*, Won Kim*, Maureen Hanratty* Department of Electrical Engineering and Computer Sciences
More informationSection 2: Lithography. Jaeger Chapter 2 Litho Reader. The lithographic process
Section 2: Lithography Jaeger Chapter 2 Litho Reader The lithographic process Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered with silicon dioxide barrier layer Positive photoresist
More informationLine End Shortening. T h e L i t h o g r a p h y E x p e r t (Spring 2000) Chris A. Mack, FINLE Technologies, Austin, Texas
Tutor29.doc: Version 2/15/00 Line End Shortening Chris A. Mack, FINLE Technologies, Austin, Texas T h e L i t h o g r a p h y E x p e r t (Spring 2000) Historically, lithography engineering has focused
More informationimmersion optics Immersion Lithography with ASML HydroLith TWINSCAN System Modifications for Immersion Lithography by Bob Streefkerk
immersion optics Immersion Lithography with ASML HydroLith by Bob Streefkerk For more than 25 years, many in the semiconductor industry have predicted the end of optical lithography. Recent developments,
More informationAdvanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP-FOPLP Processing
Advanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP-FOPLP Processing Keith Best, Gurvinder Singh, and Roger McCleary Rudolph Technologies, Inc. 16 Jonspin Rd. Wilmington,
More informationSection 2: Lithography. Jaeger Chapter 2 Litho Reader. EE143 Ali Javey Slide 5-1
Section 2: Lithography Jaeger Chapter 2 Litho Reader EE143 Ali Javey Slide 5-1 The lithographic process EE143 Ali Javey Slide 5-2 Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered
More informationCharacterization Study of an Aqueous Developable Photosensitive Polyimide on 300 mm Wafers
Characterization Study of an Aqueous Developable Photosensitive Polyimide on 300 mm Wafers Warren W. Flack, Scott Kulas Ultratech Stepper, Inc. San Jose, CA 95134 Craig Franklin HD Microsystems Austin,
More informationUsing the Normalized Image Log-Slope, part 2
T h e L i t h o g r a p h y E x p e r t (Spring ) Using the Normalized Image Log-Slope, part Chris A. Mack, FINLE Technologies, A Division of KLA-Tencor, Austin, Texas As we saw in part of this column,
More informationSection 2: Lithography. Jaeger Chapter 2. EE143 Ali Javey Slide 5-1
Section 2: Lithography Jaeger Chapter 2 EE143 Ali Javey Slide 5-1 The lithographic process EE143 Ali Javey Slide 5-2 Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered with silicon
More informationCopyright 2000 by the Society of Photo-Optical Instrumentation Engineers.
Copyright 2000 by the Society of Photo-Optical Instrumentation Engineers. This paper was published in the proceedings of the 20 th Annual BACUS Symposium on Photomask Technology SPIE Vol. 4186, pp. 503-507.
More informationWhat s So Hard About Lithography?
What s So Hard About Lithography? Chris A. Mack, www.lithoguru.com, Austin, Texas Optical lithography has been the mainstay of semiconductor patterning since the early days of integrated circuit production.
More informationOptical Proximity Effects, part 2
T h e L i t h o g r a p h y E x p e r t (Summer 1996) Optical Proximity Effects, part 2 Chris A. Mack, FINLE Technologies, Austin, Texas In the last edition of the Lithography Expert, we examined one type
More informationEE143 Fall 2016 Microfabrication Technologies. Lecture 3: Lithography Reading: Jaeger, Chap. 2
EE143 Fall 2016 Microfabrication Technologies Lecture 3: Lithography Reading: Jaeger, Chap. 2 Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1-1 The lithographic process 1-2 1 Photolithographic
More informationRudolph s JetStep Lithography System Maximizes Throughput while Addressing the Specific Challenges of Advanced Packaging Applications
Rudolph s JetStep Lithography System Maximizes Throughput while Addressing the Specific Challenges of Advanced Packaging Applications Elvino da Silveira - Rudolph Technologies, Inc. ABSTRACT Rudolph s
More informationCopyright 2000 by the Society of Photo-Optical Instrumentation Engineers.
Copyright by the Society of Photo-Optical Instrumentation Engineers. This paper was published in the proceedings of Optical Microlithography XIII, SPIE Vol. 4, pp. 658-664. It is made available as an electronic
More informationAnalysis of Focus Errors in Lithography using Phase-Shift Monitors
Draft paper for SPIE Conference on Microlithography (Optical Lithography) 6/6/2 Analysis of Focus Errors in Lithography using Phase-Shift Monitors Bruno La Fontaine *a, Mircea Dusa **b, Jouke Krist b,
More informationUV LED ILLUMINATION STEPPER OFFERS HIGH PERFORMANCE AND LOW COST OF OWNERSHIP
UV LED ILLUMINATION STEPPER OFFERS HIGH PERFORMANCE AND LOW COST OF OWNERSHIP Casey Donaher, Rudolph Technologies Herbert J. Thompson, Rudolph Technologies Chin Tiong Sim, Rudolph Technologies Rudolph
More informationModule 11: Photolithography. Lecture 14: Photolithography 4 (Continued)
Module 11: Photolithography Lecture 14: Photolithography 4 (Continued) 1 In the previous lecture, we have discussed the utility of the three printing modes, and their relative advantages and disadvantages.
More informationManaging Within Budget
Overlay M E T R O L OProcess G Y Control Managing Within Budget Overlay Metrology Accuracy in a 0.18 µm Copper Dual Damascene Process Bernd Schulz and Rolf Seltmann, AMD Saxony Manufacturing GmbH, Harry
More informationPhotolithography Technology and Application
Photolithography Technology and Application Jeff Tsai Director, Graduate Institute of Electro-Optical Engineering Tatung University Art or Science? Lind width = 100 to 5 micron meter!! Resolution = ~ 3
More informationLithography. 3 rd. lecture: introduction. Prof. Yosi Shacham-Diamand. Fall 2004
Lithography 3 rd lecture: introduction Prof. Yosi Shacham-Diamand Fall 2004 1 List of content Fundamental principles Characteristics parameters Exposure systems 2 Fundamental principles Aerial Image Exposure
More informationOptical Microlithography XXVIII
PROCEEDINGS OF SPIE Optical Microlithography XXVIII Kafai Lai Andreas Erdmann Editors 24-26 February 2015 San Jose, California, United States Sponsored by SPIE Cosponsored by Cymer, an ASML company (United
More informationApplications of Maskless Lithography for the Production of Large Area Substrates Using the SF-100 ELITE. Jay Sasserath, PhD
Applications of Maskless Lithography for the Production of Large Area Substrates Using the SF-100 ELITE Executive Summary Jay Sasserath, PhD Intelligent Micro Patterning LLC St. Petersburg, Florida Processing
More informationOptimizing FinFET Structures with Design-based Metrology
Lithography M e t r o l o g y Optimizing FinFET Structures with Design-based Metrology Tom Vandeweyer, Christie Delvaux, Johan De Backer, and Monique Ercken, IMEC Gian Lorusso, Radhika Jandhyala, Amir
More informationDesign Rules for Silicon Photonics Prototyping
Design Rules for licon Photonics Prototyping Version 1 (released February 2008) Introduction IME s Photonics Prototyping Service offers 248nm lithography based fabrication technology for passive licon-on-insulator
More informationSilicon Photonics Technology Platform To Advance The Development Of Optical Interconnects
Silicon Photonics Technology Platform To Advance The Development Of Optical Interconnects By Mieke Van Bavel, science editor, imec, Belgium; Joris Van Campenhout, imec, Belgium; Wim Bogaerts, imec s associated
More informationOutline. 1 Introduction. 2 Basic IC fabrication processes. 3 Fabrication techniques for MEMS. 4 Applications. 5 Mechanics issues on MEMS MDL NTHU
Outline 1 Introduction 2 Basic IC fabrication processes 3 Fabrication techniques for MEMS 4 Applications 5 Mechanics issues on MEMS 2.2 Lithography Reading: Runyan Chap. 5, or 莊達人 Chap. 7, or Wolf and
More informationCopyright 1998 by the Society of Photo-Optical Instrumentation Engineers.
Copyright 998 by the Society of Photo-Optical Instrumentation Engineers. This paper was published in the proceedings of the 8 th Annual BACUS Symposium on Photomask Technology and Management SPIE Vol.
More informationAdvanced Stepper Lithography Technology to Enable Flexible AMOLED Displays. Keith Best Roger McCleary Elvino M da Silveira 5/19/17
Advanced Stepper Lithography Technology to Enable Flexible AMOLED Displays Keith Best Roger McCleary Elvino M da Silveira 5/19/17 Agenda About Rudolph JetStep G System overview and performance Display
More informationi- Line Photoresist Development: Replacement Evaluation of OiR
i- Line Photoresist Development: Replacement Evaluation of OiR 906-12 Nishtha Bhatia High School Intern 31 July 2014 The Marvell Nanofabrication Laboratory s current i-line photoresist, OiR 897-10i, has
More informationMicro-Optic Solar Concentration and Next-Generation Prototypes
Micro-Optic Solar Concentration and Next-Generation Prototypes Jason H. Karp, Eric J. Tremblay and Joseph E. Ford Photonics Systems Integration Lab University of California San Diego Jacobs School of Engineering
More informationImproving registration metrology by correlation methods based on alias-free image simulation
Improving registration metrology by correlation methods based on alias-free image simulation D. Seidel a, M. Arnz b, D. Beyer a a Carl Zeiss SMS GmbH, 07745 Jena, Germany b Carl Zeiss SMT AG, 73447 Oberkochen,
More informationDefense Technical Information Center Compilation Part Notice
UNCLASSIFIED Defense Technical Information Center Compilation Part Notice ADP012609 TITLE: Scatterometry for Lithography Process Control and Characterization in IC Manufacturing DISTRIBUTION: Approved
More informationIndex. Cambridge University Press Silicon Photonics Design Lukas Chrostowski and Michael Hochberg. Index.
absorption, 69 active tuning, 234 alignment, 394 396 apodization, 164 applications, 7 automated optical probe station, 389 397 avalanche detector, 268 back reflection, 164 band structures, 30 bandwidth
More informationApplication-Based Opportunities for Reused Fab Lines
Application-Based Opportunities for Reused Fab Lines Semicon China, March 17 th 2010 Keith Best Simax Lithography S I M A X A L L I A N C E P A R T N E R S Outline Market: Exciting More than Moore applications
More informationInspection of templates for imprint lithography
Inspection of templates for imprint lithography Harald F. Hess, a) Don Pettibone, David Adler, and Kirk Bertsche KLA-Tencor 160 Rio Robles, San Jose, California 95134 Kevin J. Nordquist, David P. Mancini,
More informationLithography. Development of High-Quality Attenuated Phase-Shift Masks
Lithography S P E C I A L Development of High-Quality Attenuated Phase-Shift Masks by Toshihiro Ii and Masao Otaki, Toppan Printing Co., Ltd. Along with the year-by-year acceleration of semiconductor device
More informationThermography. White Paper: Understanding Infrared Camera Thermal Image Quality
Electrophysics Resource Center: White Paper: Understanding Infrared Camera 373E Route 46, Fairfield, NJ 07004 Phone: 973-882-0211 Fax: 973-882-0997 www.electrophysics.com Understanding Infared Camera Electrophysics
More informationMICROBUMP CREATION SYSTEM FOR ADVANCED PACKAGING APPLICATIONS
MICROBUMP CREATION SYSTEM FOR ADVANCED PACKAGING APPLICATIONS Andrew Ahr, EKC Technology, & Chester E. Balut, DuPont Electronic Technologies Alan Huffman, RTI International Abstract Today, the electronics
More informationSilicon Interposers enable high performance capacitors
Interposers between ICs and package substrates that contain thin film capacitors have been used previously in order to improve circuit performance. However, with the interconnect inductance due to wire
More informationThrough Glass Via (TGV) Technology for RF Applications
Through Glass Via (TGV) Technology for RF Applications C. H. Yun 1, S. Kuramochi 2, and A. B. Shorey 3 1 Qualcomm Technologies, Inc. 5775 Morehouse Dr., San Diego, California 92121, USA Ph: +1-858-651-5449,
More informationMutually Optimizing Resolution Enhancement Techniques: Illumination, APSM, Assist Feature OPC, and Gray Bars
Mutually Optimizing Resolution Enhancement Techniques: Illumination, APSM, Assist Feature OPC, and Gray Bars Bruce W. Smith Rochester Institute of Technology, Microelectronic Engineering Department, 82
More informationDIY fabrication of microstructures by projection photolithography
DIY fabrication of microstructures by projection photolithography Andrew Zonenberg Rensselaer Polytechnic Institute 110 8th Street Troy, New York U.S.A. 12180 zonena@cs.rpi.edu April 20, 2011 Abstract
More informationLecture 7. Lithography and Pattern Transfer. Reading: Chapter 7
Lecture 7 Lithography and Pattern Transfer Reading: Chapter 7 Used for Pattern transfer into oxides, metals, semiconductors. 3 types of Photoresists (PR): Lithography and Photoresists 1.) Positive: PR
More informationACOUSTIC MICRO IMAGING ANALYSIS METHODS FOR 3D PACKAGES
ACOUSTIC MICRO IMAGING ANALYSIS METHODS FOR 3D PACKAGES Janet E. Semmens Sonoscan, Inc. Elk Grove Village, IL, USA Jsemmens@sonoscan.com ABSTRACT Earlier studies concerning evaluation of stacked die packages
More information45nm Foundry CMOS with Mask-Lite Reduced Mask Costs
This work is sponsored in part by the Air Force Research Laboratory (AFRL/RVSE) 45nm Foundry CMOS with Mask-Lite Reduced Mask Costs 21 March 2012 This work is sponsored in part by the National Aeronautics
More information3D TSV Micro Cu Column Chip-to-Substrate/Chip Assmbly/Packaging Technology
3D TSV Micro Cu Column Chip-to-Substrate/Chip Assmbly/Packaging Technology by Seung Wook Yoon, *K. T. Kang, W. K. Choi, * H. T. Lee, Andy C. B. Yong and Pandi C. Marimuthu STATS ChipPAC LTD, 5 Yishun Street
More informationPackaging Fault Isolation Using Lock-in Thermography
Packaging Fault Isolation Using Lock-in Thermography Edmund Wright 1, Tony DiBiase 2, Ted Lundquist 2, and Lawrence Wagner 3 1 Intersil Corporation; 2 DCG Systems, Inc.; 3 LWSN Consulting, Inc. Addressing
More informationEE-527: MicroFabrication
EE-57: MicroFabrication Exposure and Imaging Photons white light Hg arc lamp filtered Hg arc lamp excimer laser x-rays from synchrotron Electrons Ions Exposure Sources focused electron beam direct write
More informationDecomposition difficulty analysis for double patterning and. the impact on photomask manufacturability
Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability Yuichi Inazuki 1*, Nobuhito Toyama, Takaharu Nagai 1, Takanori Sutou 1, Yasutaka Morikawa 1, Hiroshi
More informationUnderstanding Infrared Camera Thermal Image Quality
Access to the world s leading infrared imaging technology Noise { Clean Signal www.sofradir-ec.com Understanding Infared Camera Infrared Inspection White Paper Abstract You ve no doubt purchased a digital
More informationOptical Lithography. Here Is Why. Burn J. Lin SPIE PRESS. Bellingham, Washington USA
Optical Lithography Here Is Why Burn J. Lin SPIE PRESS Bellingham, Washington USA Contents Preface xiii Chapter 1 Introducing Optical Lithography /1 1.1 The Role of Lithography in Integrated Circuit Fabrication
More informationMass transfer with elastomer stamps for microled displays.
Frontiers in Assembly Mass transfer with elastomer stamps for microled displays. Matt Meitl X-Celeprint, Inc. mmeitl@x-celeprint.com 1 The best materials for the best displays The materials identify the
More informationOptical Requirements
Optical Requirements Transmission vs. Film Thickness A pellicle needs a good light transmission and long term transmission stability. Transmission depends on the film thickness, film material and any anti-reflective
More informationImec pushes the limits of EUV lithography single exposure for future logic and memory
Edition March 2018 Semiconductor technology & processing Imec pushes the limits of EUV lithography single exposure for future logic and memory Imec has made considerable progress towards enabling extreme
More informationIntegrated Focusing Photoresist Microlenses on AlGaAs Top-Emitting VCSELs
Integrated Focusing Photoresist Microlenses on AlGaAs Top-Emitting VCSELs Andrea Kroner We present 85 nm wavelength top-emitting vertical-cavity surface-emitting lasers (VCSELs) with integrated photoresist
More informationOrganic Antireflective Coatings for Photomask Fabrication using Optical Pattern Generators
Organic Antireflective Coatings for Photomask Fabrication using Optical Pattern Generators Benjamen M. Rathsack 1, Cyrus E. Tabery 1, Cece Philbin 2, and C. Grant Willson 1 September 15, 1999 1 Department
More informationMICROMACHINED INTERFEROMETER FOR MEMS METROLOGY
MICROMACHINED INTERFEROMETER FOR MEMS METROLOGY Byungki Kim, H. Ali Razavi, F. Levent Degertekin, Thomas R. Kurfess G.W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta,
More informationRegistration performance on EUV masks using high-resolution registration metrology
Registration performance on EUV masks using high-resolution registration metrology Steffen Steinert a, Hans-Michael Solowan a, Jinback Park b, Hakseung Han b, Dirk Beyer a, Thomas Scherübl a a Carl Zeiss
More informationIMEC update. A.M. Goethals. IMEC, Leuven, Belgium
IMEC update A.M. Goethals IMEC, Leuven, Belgium Outline IMEC litho program overview ASML ADT status 1 st imaging Tool description Resist projects Screening using interference litho K LUP / Novel resist
More informationContrast Enhancement Materials CEM 365HR
INTRODUCTION In 1989 Shin-Etsu Chemical acquired MicroSi, Inc. including their Contrast Enhancement Material (CEM) technology business*. A concentrated effort in the technology advancement of a CEM led
More informationCritical Dimension Enhancement of DUV Photolithography on the ASML 5500/300. Francesca Calderon Miramonte High School August 13th, 2015
Critical Dimension Enhancement of DUV Photolithography on the ASML 5500/300 Francesca Calderon Miramonte High School August 13th, 2015 1 g-line - 436 nm i-line - 365 nm DUV - 248 nm DUV - 193 nm resolution
More informationChapter 3 Fabrication
Chapter 3 Fabrication The total structure of MO pick-up contains four parts: 1. A sub-micro aperture underneath the SIL The sub-micro aperture is used to limit the final spot size from 300nm to 600nm for
More informationPerformance data of a new 248 nm CD metrology tool proved on COG reticles and PSM s
Performance data of a new 248 nm CD metrology tool proved on COG reticles and PSM s Gerhard Schlueter a, Walter Steinberg a, John Whittey b a Leica Microsystems Wetzlar GmbH Ernst-Leitz-Str. 17-37, D-35578
More information200mm and 300mm Test Patterned Wafers for Bonding Process Applications SKW ASSOCIATES, INC.
C M P C h a r a c t e r I z a t I o n S o l u t I o n s 200mm and 300mm Test Patterned Wafers for Bonding Process Applications SKW ASSOCIATES, INC. 2920 Scott Blvd., Santa Clara, CA 95054 Tel: 408-919-0094,
More informationTechnology for the MEMS processing and testing environment. SUSS MicroTec AG Dr. Hans-Georg Kapitza
Technology for the MEMS processing and testing environment SUSS MicroTec AG Dr. Hans-Georg Kapitza 1 SUSS MicroTec Industrial Group Founded 1949 as Karl Süss KG GmbH&Co. in Garching/ Munich San Jose Waterbury
More informationPhotolithography II ( Part 2 )
1 Photolithography II ( Part 2 ) Chapter 14 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Saroj Kumar Patra, Department of Electronics and Telecommunication, Norwegian University of Science
More informationComprehensive Simulation of E-beam Lithography Processes Using PROLITH/3D and TEMPTATION Software Tools
Comprehensive Simulation of E-beam Lithography Processes Using PROLITH/3D and TEMPTATION Software Tools I. Yu. Kuzmin, C. A. Mack* Soft Services, Djalila 5-2-507,Moscow 115580, Russia *FNLE Division ofkla-tencor,
More information