An Application of DMADV Methodology for Increasing the Yield Rate of CMOS Camera

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1 -ICIT 9-/4/7 in RoC Going for Gold ~ 5-S, 6-σ & KM Paper #: 3-6 Page- /7 An Application of MAV Methodology for Increasing the Yield Rate of CMOS Caera Tsang-Chuan Chang r. Chiao-Tzu Huang Prof. K. S. Chen 3,,3 epartent of Industrial Engineering and Manageent, ational Chin-Yi University of Technology, Taichung, Taiwan 4. tsangchuan@hotail.co huang5@ncut.edu.tw 3 schen@ncut.edu.tw ABSTRACT Soe of Taiwan genuine products are the first position of aret share around the world, and there are also any copetitors show their capability in challenging the position of Taiwan anufacture. The strategy for products in the stage of aturity under steep copetition is to increase their quality and yield rate which will prevent unnecessary waste. There are soe researches about adopting Six Siga for iproving the yield rate of products, and the results had approved the rearable outcoes. In this research, the MAV ethodology will be ipleented for iproving quality of CMOS caera, and diinishing its excess cost occurred in process. Key word: Six Siga, MAV, Soldering defects,. Introduction Motorola ipleented Six Siga copanywide in 987~997, and this practice has caused its stoc price grown ore % every year, and it also records as high as 7 billion in saving. There are any researches about Six Siga, Ha et al. ( had proposed MAIC ethodology for process iproveent, Michael(described the process of MAIC, and Motorola University developed frae wor MAV within FSS. There are also researches and cases about Six Siga practice in Taiwan, Chen et al. (5 adopted MAIC to TFT-LC Panel Quality Iproveent, Cheng (5 ipleented MAV to iprove assebly efficiency of ilitary product. The population of elders in Taiwan has caught up the rate of developed countries around the world. There are any inds of social probles, lie social welfare, edical care and social security issues had drawn forth ore attention fro governent. Since ore and ore elders need proper full attendance, edical care service provider can reotely onitor seniors daily activities with surveillance caera which is equipped with internet or wireless telecounication technology, video signal could be recorded properly for necessary review. Two of seven basic tools of quality iproveent, Pareto chart and Cause & Effect iagra will be used in this research for finding priary causes, and a quality perforance index would be proposed to easure soldering defective rate. As soon as the priary causes been identified, redesign the ey coponents or process iproveent need to be carried out. Thru repeatedly test and verification, the purpose of this research is following Six Siga systeatic practice to efficiently reduce defective rate and iprove the level of quality. Soldering defects will occur in anual soldiering process and process of autoatic surface ounting (SMT, achine setup, negligence of operator, iproper soldering tie and iproper soldering teperature all possible cause the defects. Types of soldering defects could be short circuit, issing ite, wrong ite, cold soldering, insufficient soldering, wrong polarity, inaccurate positioning, circuit board distortion and so on. Soe of these causes will ae the coponents not woring properly, and the coplete CMOS caera will be identified as poor quality product. A brief description of anufacturing process for surveillance caera shown in Figure, we find there are soe quality issues being validated, which includes surface ounted process and anual soldering process. Bad quality of assebly process will cause high scale of variability happened in post process, lie no video, or video unstable etc. To find out the possible causes in assebly process, and redesign new layout, then Six Siga MAV ethodology will be ipleented for process iproveent to

2 -ICIT 9-/4/7 in RoC Going for Gold ~ 5-S, 6-σ & KM Paper #: 3-6 Page- /7 upgrade the quality of surveillance caeras. The ipleentation procedures are: efine:the goal of this research is to upgrade the quality of surveillance caera, reduce defectives rate and relieve cost of quality Measure:Measure, and identify the CTQs(Critical to Quality for surveillance caera quality. evelop an index of soldering process failure rate as an assessent odel, and then quality level of soldering process would be estiated by statistical hypothesis test. Analyze:Pareto chart and Cause & Effect diagra are adopted for analyzing possible causes esign:to iprove or delete the causes found by analysis step, redesign ey coponents or process Verify:Verify the new design of new coponent, to prove the iproveent thru hypothesis test and efficiently reduce failure rate of surveillance caera Fig. The flow diagra of SMT process for surveillance caera printed circuit board. Methodology. efine In the step of efine, quality of surveillance caera was concerned by the anufacturer, the rewor data showed high percentage of defective units happened in process, and the rewor records show that ost of rewor is caused by bad soldering oint. Therefore, this research will focus about quality level of soldering process. The bad soldering oint ay be caused by anual or SMT autoatic soldering process, achine setup, anual negligence, and iproper solder teperature setup will cause bad soldering process. Bad soldering oint will cause the coplete set of caera to unstable or no picture response.. A Measureent Model defined for bad soldering process The soldering failure rate will be defined as following:

3 -ICIT 9-/4/7 in RoC Going for Gold ~ 5-S, 6-σ & KM Paper #: 3-6 Page- 3 /7 p ( Where soldering defect rate p is defined as bad soldering counts divided by total soldering oint counts of each printed circuit board. p is the upper acceptable liit of soldering defect rate, the anufacturer could define p by itself, and it should be equal or saller than custoer s liit. U is the acceptable soldering oint defect counts liit with upper acceptable liit p. Therefore, the soldering quality index I is defined: p p I, ( p p U A soldering quality index I would be defined as: when I <, it eans that defective rate of soldering not reach liit yet; when I, it eans that defective rate of soldering ust reach liit; when I > it eans that defective rate of soldering had exceed the axiu liit. Therefore, the value of I is saller, it eans that soldering process is carried out ore correctly, and the level of soldering process quality will be better. If there is an upper liit ν( where <ν < for I, then the hypothesis test would be defined as: H: I ν (Quality for soldering process is good H: I > ν (Quality for soldering process is poor If the test approves the null hypothesis, then the quality level of soldering process eets the requireent, otherwise the quality level of soldering process did not eet the requireent. Since every PCB has the sae soldering oints, we define as. Then bad soldering rate for th sapling is defined as p, and its estiator is: pˆ (3 Which ~ B(, p, let,, represent saplings have been collected, the average bad soldering rate: pˆ p The estiator of th sapling: And average soldering quality index I for saplings: Then expected value and variance of Î would be:, (4 pˆ pˆ, (5 p p U, (6 U E( E( E( I, (7 U U U V ( Apparently, V ( V ( U ( U ( I (, (8 U U Î is the best Uniforly Miniu Variance Unbiased Estiator (UMVUE of I

4 -ICIT 9-/4/7 in RoC Going for Gold ~ 5-S, 6-σ & KM Paper #: 3-6 Page- 4 /7 - I Let Z, (9 I ( U When saple size is large enough, then Central Liit Theore shows that rando variable Z would be approxiate to a standardized noral distribution. For sapling, and each value Î for each sapling,,, and Î is the average value of saplings. Suppose w, ( According to I ˆ w then p-value w - v P( Z Φ( z v( U Φ is the oral standardized cuulative distribution function. The rules for easureent will be defined as following:. p-value<. : it eans that CMOS caera anufacturer has very significant not capable of soldering process, it should address on iproving its previous process, find out the causes, and possible solution proect for eliinating this dilea should be proposed... p-value<. 5 : it eans that CMOS caera anufacturer has significant not capable of soldering process, there is roo for iproving, it should revised its quality level to ideal target value. 3. p-value. 5 : it eans that CMOS caera anufacturer has capable of soldering process, it is unnecessary to iprove the process iediately, continuous onitor the process and eep the quality level of CMOS caera for its copetition..3 Analyze In the step of analyze, Pareto chart and Cause & Effect iagra are adopted to find out all possible causes. There is a suarized for test record of video response shown in Fig. Apparently, the vital portion of unacceptable quality perforance coes into 68.7% (no response of total defective units, and the second large portion coes into 7.% (video unstable of total defective units. The reasons for no video response are solder bridging between two oints, or insufficient solder. The defective crystal quartz or crac found on the CMOS unit also causes no video response in quality test. Poor anual touch up solder for power/ signal line, and poor connector wor will cause video unstable. Therefore, in order to iprove the quality of caera, causes ust be found out, this research had checed and reviewed 68 defective units fro lots, and categorized four aor rewor types:.manual touch up solder;.replace power/video line 3.Replace quartz; 4.Replaces CMOS. And, 39 units (89.% belonged to type, Replaceent aterial (power line and signal line, quartz, CMOS, occupies 9units (.8%, a rewor record shown in Figure 3.

5 -ICIT 9-/4/7 in RoC Going for Gold ~ 5-S, 6-σ & KM Paper #: 3-6 Page- 5 /7 Test Result of Video response Pareto Chart of Rewor Count RGB Test o response Video unstable Other Count Percent Cu % Percent Count Rewor Manual touch up solder CMOS IC change Quartz change Other Count Percent Cu % Percent Fig Test record of Video response Fig 3 Rewor record for defective unit As a result, we find that bad soldering quality is the aor cause of video response unstable, oscillation, and power interittent. To explore all the potential causes that result in the bad soldering, and propose a possible solution to iprove the quality level of CMOS caeras. A cause & effect iagra shown in Fig.4 is adopted to find the potential causes, the size of printed circuit board is restricted according its design constrain which cause the soldering oints of coponents too close. The oints are too close to each other will be very coplicated for operator; iproper soldering process will coe with short circuit, isalignent, pin hole, cold soldering, and uneven soldering. The proect tea spent tie in elaborative brainstor, the aor reason of causing bad soldering process is anual touch up oints are too close to each other, then redesign or re-layout for the circuit board need to be carried out..4 esign Fig 4 Cause & Effect diagra for poor Soldering The size of coplete circuit diagra shown in Fig.5 is liited, and it has to fit in a sall space, and increase the size of board is not possible; therefore, a redesign for printed circuit board oints is perfored shown in Fig 6. The anual touch up soldering oints designed for power and video signal purpose are replaced by a new connector shown in Fig. 7, the soldering oints will be soldered by autoatic SMT achine. Fig. 5 circuit diagra Fig. 6 Redesigned PCB layout Fig. 7 ew connector

6 -ICIT 9-/4/7 in RoC Going for Gold ~ 5-S, 6-σ & KM Paper #: 3-6 Page- 6 /7.5 Verify 3pcs of redesign units has been sapling for hypothesis test, the operator records each critical quality perforance, Table shows that only one unit is identified no video response caused by crac CMOS, and none of these is identified as video unstable or bad wire connection. Table Video response Test result with Redesigned PCB Operation Types of Causes Video response Test Count o response Video unstable 3 Bad wire connection Total Since the original design research, we find ost defective units are caused by bad soldering, then a hypothesis test is carried out for testing if defective rate is lower than the previous. Let p is the fraction about anual soldering oint rewor counts to the total defect counts, then p is defined as the rate for before redesign process, and it is.89 which is found in step of analyze; and p is defined as the rate for after redesign process, and it is which is found Table. Therefore, a hypothesis test is defined as: H : p p (Bad soldering rate not iprove H : p > p (Bad soldering rate iprove if z > z., then reect H ; and if z z.,then do not reect H where the critical value z.. 36 Since ( pˆ ˆ p ( p p z p( p p( p + n n The evidence shows there is significant iproveent of bad soldering rate, the redesigning process which was proposed by the analysis result of practicing MAV has iproved the bad soldering rate, and reduced the cost of failure rate; efficiently enhance the quality of surveillance caera. 3. Conclusion The research result shows soldering quality of printed circuit board is the ey cause of unacceptable quality of surveillance caera quality, therefore, this research applies MAV ethodology of Six Siga practice to iprove quality of anual soldering process. To help the caera anufacturer to assess if soldering quality fall in between tolerance liits, this research proposed an index as soldering process quality evaluation odel. Pareto chart, and Cause & Effect iagra are adopted to find the aor causes of poor quality, then process of redesigning the ey coponent, and process will be conducted. The final verification and test had showed that MAV ethodology had reduced the bad soldering rate. This research ay provide a solution of practicing MAV, and then caera anufacturer could iprove its product quality. Reference Chen, K. S., Wang, C. H. and Chen, H. T., [5]. A MAIC Approach to TFT-LC Panel Quality Iproveent, Microelectronics & Reliability. Cheng, Y. H. [5]. The iproveent of assebly efficiency of ilitary product by Six-Siga, CIT Thesis Archive,Taiwan Ha, C. H., and Lee, Y. H., []. Intelligent Integrated Plant Operation Syste for Six Siga. Annual Reviews in Control; 6, pp Michael, L. G., []. Lean Six Siga, McGraw-Hill, U.S.A. Pearson, T. A.,[ ]. Measure for Six Siga Success, Quality Progress, Vol.34 (, pp.35-4.

7 -ICIT 9-/4/7 in RoC Going for Gold ~ 5-S, 6-σ & KM Paper #: 3-6 Page- 7 /7 Peter et al.,[]. The Six Siga Way, McGraw-Hill, ew Yor. Snee, R.. and Roger W. H.,[3]. Leading Six Siga: A Step-by-Step Guide Based on Experience with GE and Other Six Siga Copanies, Upper Saddle River,.J.: Pearson Education. Antony, J., Kuar M., Madu, C.., 5, Six siga in sall-and-ediu-sized UK anufacturing enterprises, International Journal of Quality & Reliability Manageent, Vol.(8, pp Authors Bacground Mr. Tsang-Chuan Chang currently enrolled his second year of graduate school of Industrial Engineering and Manageent. His aor interests are Statistics, Six Siga anageent and Quality anageent. r. Chiao-Tzu Huang is currently an Associate Professor in the Institute of Industrial Engineering and Manageent, ational Chinyi University of Technology, Taiping, Taiwan 4, R.O.C., He received his Ph.. in Industrial Engineering fro University of Texas at Arlington, USA. His research interests are Statistical Process Control, Autoation, and Quality anageent. Prof. K. S. Chen is currently President of ational Chinyi University of Technology, Taiping, Taiwan 4, R.O.C., He received his Ph.. in Industrial Engineering and Manageent fro ational Chiao Tung University, Hsinchu, Taiwan. His research interests are Statistical Process Control, Process Capability Indices, and Quality anageent.