More-than-Moore 2.5D and 3D SiP Integration

Transcription

1 More-than-Moore 2.5D and 3D SiP Integration

2 Riko Radojcic More-than-Moore 2.5D and 3D SiP Integration 123

3 Riko Radojcic San Diego, CA USA ISBN ISBN (ebook) DOI / Library of Congress Control Number: Springer International Publishing AG 2017 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

4 Preface There is a lot of buzz in the industry about More-than-Moore technology directions, and especially the 2.5D and 3D System in Package (SiP) integration options. In principle, More-than-Moore integration, and 2.5D and 3D SiP implementation, is an opportunity that can be leveraged to extend system level miniaturization without More-Moore type of scaling, and to bring incremental cost-power-performance value. At a superficial level, it would appear that the SiP concept of integrating multiple die in a package either by putting them side by side (2.5D integration) or on top of each other (3D integration) is pretty straightforward, and not all that novel. This would seem especially so now that the key enabling foundational technology modules, such as the Through Si Vias and the ubumps, have been proven out, and are in volume manufacturing. After all, there are several announced SiP products that leverage the 2.5D and 3D integration technologies, and more are rumored to be coming. So, what is the big deal? However, in practice, implementation of competitive 2.5D and 3D SiPs for mainstream products especially for cost conscious consumer market is challenging. The entire IC product design and sourcing ecosystem, and the standard industry practices and methodologies, have all been optimized over the last few decades for sourcing 2D SoC type of products, and are therefore challenged by some of the requirements for, and uniqueness of, 2.5D and 3D SiPs. Thus, adoption of 2.5D and 3D technologies is disruptive to the standard industry paradigms. The intent of this book is to explore the tradeoffs that need to be considered in order to make 2.5D and/or 3D integration technologies attractive for use in high volume IC components targeting consumer products, competing in, for example, the mobile market. The new degrees of freedom offered, as well as the new constraints imposed by these integration technologies are in fact quite insidious. The tradeoffs required to optimize a 2.5D or 3D SiP products and make them competitive versus traditional 2D SoC IC are complex, mutually interdependent, involve architecture, design, Si and package technologies, have consequences in multiple physical domains, and impact both the technical and business considerations. It IS complicated! v

5 vi Preface This book therefore reviews the various popular technology options for both 2.5D and 3D integration, with focus on the candidates that are productizable within a 3- to 5-year implementation horizon. Basic manufacturing process flows, and the associated supply chain, required to realize a competitive SiP product are summarized. 2.5D SiP integration options based on Si, Organic Substrate, or Glass Interposers, or on Fan Out Wafer Level Package technology, are all reviewed. 3D SiP integration based on Through Si Via chip stacking, including the various technology and stacking options are presented. The value propositions of 2.5D and/or 3D integration are outlined, with a focus on monetization opportunities in high volume consumer marketspace. The potential system-level benefits of tighter memory integration either via an HBM stack in a 2.5D package or WideIO in a 3D package are presented. The opportunity of improving component-level cost structure through splitting a mono-die SoC into a Split Die SiP are explored. The 2.5D and 3D SiP architecture, physical design, Si and Package process technology, and product sourcing tradeoffs and considerations are explored, and the effects of the differences between 2.5D/3D integration versus 2D SoC are amplified. The upgrades to the design methodologies and EDA tools required to optimize 2.5D and 3D SiPs are identified, and some practical short cut solutions are proposed. The impact of 2.5D and 3D integration on electrical performance as well as on the thermal and mechanical stress characteristics, are described, and methodologies for addressing the potential interactions are outlined. Typical standard practices used in making new IC product development decisions, as well as the structure of the typical corporate entities involved in sourcing IC products, are also reviewed, and the business implications of adopting a disruptive More-than-Moore type of technology are assessed. Thus, this book provides a holistic perspective that spans the broad process and the design technologies and methodologies, and addresses both, the technical and business considerations. It is not quite an everything-you-always-wanted-toknow-about-2.5d/3d-technology-but-were-afraid-to-ask type of work, but it does elaborate on why adoption of More-than-Moore type of 2.5D and 3D integration technologies is complicated. It can be done, but it is complicated San Diego, USA Riko Radojcic

6 Acknowledgements The learning described in this book is a result of an effort to evaluate the 2.5D and 3D integration opportunities for semiconductor products competing in the consumer mobile market. The effort was a multi-company collaboration that spanned several years and involved several excellent forward looking multidisciplinary engineering teams. As such, it is not possible to name all the companies, teams or individuals who have contributed in different and significant ways but a big thank you is due to all. However, the author would like to recognize the outstanding effort, and talent, of the Advanced Technology Integration team at Qualcomm, who were at the center of these 2.5D and 3D evaluations. Furthermore, this work would not be complete without naming a few colleagues, nor would it be fair to ignore the outstanding contributors and teachers amongst them. So, a special kudos and thank you is owed to Matt Nowak, Sam Gu, Durodami Lisk, Brian Henderson, Urmi Ray, Mark Nakamoto, Anup Keval, Maxime Leclercq, Rajiv Dunne, Karthikeyan Dhandapani, Wei Zhao, Juzer Fatehi, Magesh Govindarajan, Ilya Gindentuller, Dong Wook Kim, Jae Sik Lee, Ron Lindley, Miguel Miranda, Chandra Nimmagadda, Dan Perry, Vidhya Ramachandran, Thomas Toms, Martin We, Sherry Wu Thank You, one and all. It has been an honor and pleasure. vii

7 Contents 1 Introduction References More-than-Moore Technology Opportunities: 2.5D SiP Overview D SiP Technology Candidates Through-Si Interposer (TSI) Low-Cost Si Interposer (LCIs) Photo-Defined Organic Interposer (POI) Low-Cost Glass Interposer (LCIg) Fan Out WLP Hybrid Technologies (SLIT, SLIM) D SiP Technology Value Propositions System Integration Value Proposition Split Die SiP Value Proposition Small Die SiP Value Propositions D SiP Technology Tradeoffs Architecture Knobs Physical Design Knobs Si Technology Knobs Packaging Technology Knobs Test Knobs D SiP Technology Solutions D Technology Solutions for Integrated SiP D Technology Solutions for Area-Based Split Die SiP D Technology Solutions for Small Die SiP References ix

8 x Contents 3 More-than-Moore Technology Opportunities: 3D SiP Overview D SiP Technology Options Requirements TSV Formation TSV Integration with CMOS Flow TSV Integration with Assembly Flow D SiP Technology Value Propositions Homogenous 3D SiP Integration Value Proposition Heterogeneous 3D SiP Integration Value WideIO Memory Value Proposition D SiP Technology Tradeoffs Architecture Knobs Application Knobs Physical Design Knobs TSV Technology Knobs D SiP Technology Solutions D Technology Solutions for Heterogeneous M-o-L Integration D Technology Solutions for Homogeneous and/or Heterogenous L-o-L Integration References More-than-Moore Design Eco-System Overview More-than-Moore Architectural Opportunities Architecture Concepts Physical Partitioning Concepts More-than-Moore Design for Multi-Physics Opportunities Challenges Infrastructure Requirements Thermal Management Mechanical Stress Management Electrical Interaction Management More-than-Moore Design Methodology Opportunities Design Methodology Requirements Ideal Design Methodology Requirements Practical Design Methodology Current Status More-than-Moore Modeling and Characterization Opportunities Test Chip Strategy Test Chip Content Characterization and Models References

9 Contents xi 5 More-than-Moore Adoption Landscape Business Development Landscape The Cast The Plot Technology Development Landscape Landscape for More-Moore Scaling Landscape for More-than-Moore Scaling Product Development Landscape Technology Intersect Schedule Conundrum Cost Projection Conundrum Risk Conundrum Benefit Conundrum Observations and Opinions Product Sector Drivers Mobile Sector Drivers Concluding Remarks Index

10 Definition of Acronyms ASP AUC BEOL BGA BLR CFD CPI CTE CVD D2D DDR DFT DRM EDA FCBGA FEM FEOL FOM HBM HMC HVM I/O KGD KoZ L-o-L LPDDR LVM MCM MEOL MM M-o-L Average Selling Price Average Unit Cost Back End of Line Ball Grid Array Board Level Reliability Computational Fluid Dynamics Chip-Package Interaction Coefficient of Thermal Expansion Chemical Vapor Deposition Die-to-Die Double Data Rate Design for Test Design Rule Manual Electronic Design Automation Flip Chip Ball Grid Array Finite Element Model Front End of Line Figure of Merit High Bandwidth Memory Hybrid Memory Cube High Volume Manufacturing Input-Output Known Good Die Keep out Zone Logic-on-Logic Low Power DDR Low Volume Manufacturing Multi Chip Module Middle End of Line More-Moore Memory-on-Logic xiii

11 xiv Definition of Acronyms MtM OSAT P/G PCB PDK PDN PI PoP RDL SAP SI SiP SoC T2T TCB TDDB TGV TMV TSV UBM More-than-Moore Outsourced Semiconductor Assembly and Test Power and Ground Printed Circuit Board Process Design Kit Power Distribution Network Power Integrity Package-on-Package Re-Distribution Layer Semi-Additive Process Signal Integrity System-in-Package System-on-Chip Tier-to-Tier Thermal Compression Bonding Temporary Bond and De-Bond Through Glass Via Through Mold Via Through Si Via Under Bump Metallization

12 Definition of Terms Technology is a generic term, but here often refers to manufacturing process technologies, including Si wafer processing, assembly and packaging processing, and the associated design enablement. Incumbent Technology refers to technologies that are an evolutionary derivatives of an existing mainstream technology used in current products in an existing market, and with an easy projected value proposition. For example, scaling CMOS technology from node n to node n + 1, along the More-Moore path, is an incumbent technology solution. Similarly pushing package substrate technology from 10 to 8 um line/space spec purely through improvements in process and materials is an incumbent technology solution. And so on. Disruptive Technology refers to technologies that break a trend in technology evolution and/or roadmaps and require a change in product architecture and/or the design to generate a value proposition. For example, TSV-based 3D stacking is a disruptive technology solution. WideIO memory is disruptive relative to LPDDR memory. And so on. Value Proposition refers to the balance of the cost-benefit equation, and the analyses of the various elements that contribute to the cost and/or benefit for a product is referred to as tradeoff assessment. i.e., conceptually: Value = (Benefit) (Cost). Terms like Strata or Levels or Floors have been used in the industry to refer to the individual levels in a 3D stack. Here the term used is Tier. The bottom die is referred to as Tier 1 (T1), next is Tier 2 (T2), etc. Term Die-to-Die (D2D) is used to denote die interconnections for 2.5D side by side integration and Tier-to-Tier (T2T) is used to denote die interconnections for 3D stacked integration. Partitioning refers to different ways of distributing existing functions in a system (e.g., CPU, GPU, PHY, Memory, etc ) across a die or a system. Conventionally a system contains for example a Digital die (with CPU, GPU, Modem, etc ), DRAM, a non-volatile Memory, some display drivers, a PMIC, etc. Partitioning studies looked at different way of distributing these functions across different dice. xv