Technological Challenges in Semiconductor Lithography

Transcription

1 Technological Challenges in Semiconductor Lithography some aspects of projection lithography technology and its position in high tech industry and academia Ramin Badie ASML Research 2014

2 What do I want to share with you today Confidential Slide 2 17 February 2014 Share some general knowledge on the subject of projection lithography in the semiconductor industry from the standpoint of an ASML employee. Importance of engineering approach combined with academic knowledge in high tech industry using some examples from fluid dynamics and heat transfer in lithography tools. Some personal thoughts on the successes of ASML and its way of working in the lithography market. Discussion on the role of the high tech industry in the Netherlands.

3 Billion 50 Anything will be connected! that can benefit form connection THINGS Source: Ericsson, ISS Europe, Feb 2011 Inflection points for our industry PEOPLE PLACES

4 Integrated Circuits (chips) are integrated in our societal use Slide 4 16 October 2013

5 IC units, in billions Data: WSTS More than 180 billion chips are made every year Total IC units In 2012, 185 billion chips were produced 27 for every man, woman and child on the planet. Slide 5 16 October 2013

6 1947 The Point contact transistor Bell Labs How it all got started The First IC Texas Instruments 1961 The First Planar IC Fairchild

7 Slide 7

8 Lithography enables affordable connected electronics, improving quality of life and sustainability Slide 8 January 2013 $1,469 B Electronic Applications in 2012 $1,423 B in 2011, $1,343 B in 2010 $ 6.5 B Semiconductor Litho market in 2012 $8.2 B in 2011 $6.4 B in 2010 $297.6 B Semiconductor Chips in 2012 $306.8 B in 2011, $301.5 B in 2010 Source: Gartner Q4/12 and ASML

9 Driving the semiconductor industry: Moore s Statement Slide 9 16 October 2013 Gordon Moore (1965): Number of transistors per chip doubles every year. Later adjusted to two years, the trend has held for more than four decades.

10 Device roadmaps support shrink ambitions nm 16-14nm 11-10nm 8-7nm Logic Memory: 0.08um2, SRAM Device: planar or FinFET (Intel) Gate: RMG-HKMG Channel: Si Strain: stressor Vdd: 0.8V Memory: 0.05um2 SRAM Device: FinFET, FDSOI Gate: RMG-HKMG Channel: Si; (Si)Ge Strain: stressor Vdd: 0.6V Memory: 0.03um2 SRAM Device: FinFET Gate: HKMG Channel: Si, Ge, IIIV Strain: stressor Vdd: 0.5V Memory: FBRAM, STT-RAM, >8TSRAM Device: Nanowire, TFET Gate: HKMG Channel: IIIV-Graphene DRAM Flash 38-32nm Memory: stacked MIM Peri: planar Array: 6F2, bwl Gate: poly/sio2 Channel: Si Vdd=1.35V 24-19nm hp 32-28nm Memory: stacked MIM Peri: planar HKMG Array: 6F2, bwl Gate: HKMG Channel: Si Vdd=1.2V 16-14nm hp Node: 26-22nm Memory: stacked MIM Peri: planar Array: 4F2, bbl, LBL, 1T1C(VFET) Gate: HKMG Channel: Si Vdd=1.1V 13-11nm hp Node: 18-15nm Memory: FBRAM, STT-RAM, RRAM Peri: planar Array: 4F2, 1T, 1T1R, 1T1MTJ(VFET) Gate: HKMG Channel: Si Vdd~1V < 10nm hp 4.5F - 6F2 asymm. cell Density: G Device: FG Source: IMEC, ASML TDC, June 2011 ONO or CG High-k FG FG STI 6F2 asymmetric cell 4F2 symmetric cell Density: G Device: dual-fg Slide 10 7F2 asymmetric cell 4F2 symmetric cell Density: G Device:: dual-fg, Intro to BiCS, Density: > 1T with 3D chip stacking Device: 3D BiCS, XPoint-RRAM Selector: diode

11 Moore s Statement makes chips cheaper Slide October $1,162 for 1 GB 1000 NAND Flash price $/GByte $0.17 for 1 GB Source: Gartner. High quality Flash

12 and more energy-efficient Computations per Kilowatt hour double every 1.5 years Slide October 2013 Computations per kwh 1.E+16 1.E+15 1.E+14 1.E+13 1.E+12 1.E+11 1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 Univac I Eniac EDVAC SDS 920 IBM PC Cray 1 supercomputer DEC PDP-11/20 Univac II Univac III (transistors) Dell Dimension 2400 Gateway P MHz IBM PS/2E + Sun SS1000 IBM PC-AT IBM PC-XT Commodore laptops SiCortex SC5832 Dell Optiplex GXI 486/25 and 486/33 Desktops Regression results: N = 76 Adjusted R-squared = Comps/kWh = exp( x year ) Average doubling time (1946 to 2009) = 1.57 years 1.E Source: Jonathan Koomey, Lawrence Berkeley National Laboratory and Stanford University, 2009

13 Moore s statement means doing more with less Cray 1: The first supercomputer Slide October megabytes of memory 5.5 tons 150 kilowatt power supply Innovative Freon cooling system $8.8 million ($30 million in today s dollars) 1976

14 Moore s statement means doing more with less Slide October 2013 The supercomputer in your pocket: a fraction of the materials, price, power consumption

15 10 Cheaper chips drive market growth 1,000 Slide October 2013 MP3 player Flash units (in billions) Digital cameras Smart phones Solid state hard drives Flash price per GB (in dollars) Total flash units [B] Total 2001 Total 2002 Total 2003 Total 2004 Total Flash price 1 GB [$] 2005 Total 2006 Total 2007 Total 2008 Total 2009 Total 2010 Total 2011 Total 1

16 A virtuous cycle Slide October 2013

17 Everyday objects get connected Slide October 2013 GPS Fleet tracking Cash registers Smart meters Wireless IP camera

18 New devices, new applications Slide October 2013 Gyroscope (UC Irvine) Wearable sensors (Holst Centre) Camera pill with camera, transmitter and computer DNA analysis (Affymetrix) Accelerometer (IC Mechanics) Micromirrors for beamers (TI) On-Chip DNA amplification and detection (imec/panasonic) Lab on a Chip (LOC) for counting red blood cells

19 Confidential Slide February 2014 About ASML

20 ASML provides lithography equipment to produce smaller and more powerful chips Slide 20 January 2013 The Semiconductor Manufacturing Process A variety of complementary suppliers provide the other tools, materials and packaging equipment necessary to make ICs

21 ASML makes machines for making chips Lithography is the critical tool for producing chips Slide October sales: 4.73 bln More than 70 offices in 16 countries More than employees (in FTEs, payroll and flexible contracts)

22 Founded in 1984 as a spin-off from Philips Slide February 2014

23 First Philips system operational in 1975 Lens: Tulipe, Cerco (Paris) 5X reduction NA=0.26 field=10x10mm λ=436 nm resolution= 2 um Stages: hydraulic wafer:x-direction lens: Y-direction interferometric X/Y control Alignment: through the lens Focus: air pressure Wafer: 3 and 4

24 17-Feb- Slide 24

25 resulting in the systems that conquered the market In 30 years: From 1,200 nm to less than 20 nm resolution From <0.5M per system to >60M 1984: PAS 2000 Resolution: >1µm overlay: 250 nm 1989: PAS 5000 Resolution: <500 nm overlay: 100 nm 1990 s: PAS 5500 steppers/scanners Resolution: 400 to 90 nm overlay: 100 to 12 nm Slide s: Twinscan Resolution: 100 to 38 nm overlay: 20 to 4 nm 2010 s: NXE EUV systems Resolution: 32 to <20 nm overlay: 2 nm

26 Key to Moore s Law: Making smaller transistors Slide October 2013 Transistor length has shrunk by a million The first integrated circuit on silicon, on a wafer the size of a fingernail (Fairchild Semiconductor, 1959) Today: More than a billion transistors on the same area (Intel, 2012)

27 The principle of Lithography Rayleigh equation: Resolution = k 1x λ NA Slide 27

28 Lithography is at the heart of chip manufacturing Repeat 30 to 40 times to build 3 dimensional structure / Slide 28

29 Chip has more than one layer Slide 29

30 The manufacturing loop Slide October 2013 Ion implantation Stripping Deposition Etching Developing Photoresist coating Exposure

31 Fluid thinking: the liquid lens scanner Lens Air Lens Water Slide 31

32 Main Cause Class Immersion defects Droplets Droplets Particles/ Droplets Standard catalogue, put together with customers Pattern expansion Drying stains Inverted attenuation Bubbles Pattern attenuation examples Main Cause Particles Process Develop Generic Class Printed particle Bridge Micro Bridge Missing Pattern Examples Slide 32

33 Immersion Research Program: Competence Build-up In co-operation with FOM, UT, TUD, TUE, and many other European universities, academia and research centers partly within EC funded project Advanced visualization techniques of flow and temperature in micro-layers in immersion tools Application of latest theories in contact line dynamics, wetting and dewetting to immersion lithography parameters Latest theories in surface chemistry applied to immersion parameters Development of up-to-date models for understanding and better solution finding of phenomena in immersion lithography Slide 33

34 Some memorable highlights related to immersion technology in IC lithography Spring 2003: next most probable technology for 65 nm and below identified as 157 nm source dry technology and EUV (May 2003, Materials Today, Elseviers Science: Roadmap Key Challenges by A. Wolfgang, Infenion Technology) Spring 2003: ASML launched project on converting existing tool to an immersion tool November 2003: first demo immersion tool at ASML December 2003: announcement first industrial immersion lithography tool July 2005: announcement first (>1 NA) immersion tool to be shipped Q for production down to 45 nm July 2007: first shipment of highest water-based NA (1.35) enabling 38 nm technology node Q1 2008: ASML reports more than 85 immersion tools shipped since 2005 and more than half of the Q1 net sales due to immersion tools February 2010: ASML announces shipment of its 100th 1900 series (NA=1.35) immersion tools Slide 34

35 Extreme UV Lithography Slide 35

36 The future of lithography: EUV Slide October 2013 Large vacuum chamber New light source Mirror optics

37 Maintaining a clean vacuum Slide October 2013 We need to maintain a clean vacuum, but every time we expose a wafer, the photoresist releases trillions of particles

38 Firing a laser on a tin droplet 40,000 times a second Slide October 2013 Laser-Produced Plasma (LPP) source CO2 drive laser Tin droplets plasma Collector

39 Mirrors: Polished to sub-nanometer accuracy Slide October 2013 EUV mirrors are polished to an accuracy of ~50 picometers less than the diameter of a silicon atom. Blown up to the size of the Netherlands, the biggest difference in height would be less than a millimeter.

40 Confidential Slide February 2014 How does it work today at ASML?

41 A global presence Wilton (CT) Korea Slide October 2013 San Diego (CA) Veldhoven Tempe (AZ) Taiwan

42 Confidential Slide February 2014 Why is ASML considered as successful in this region?

43 Our leadership is the result of a talented workforce 49% of personnel has Master, of which approximately 500 PhDs 100% Education level Slide October % of personnel has Bachelor as highest degree 90% 80% 70% 60% R&D: >2,900 payroll + >1,400 contracted 50% 40% ASML employees >5,500 in the Netherlands 30% 20% 10% Integrated knowledge network: approximately another 20,000 jobs. More than 600 suppliers compete to offer the best technology first 0% ASML worldwide ASML Netherlands Various < Bachelor Bachelor Master Development And Engineering Research

44 Open Innovation makes complexity and cost manageable Slide October 2013 Customers Technology partners Suppliers Academia

45 Sharing risk and reward Customer firm order Shipment Suppliers bear some of the risk and participate in the rewards. Slide October 2013 Buy raw materials Manufacture modules Start system assembly Value Mutual transparency ensures that risks are well understood and minimized. QLTC sourcing model (Quality, Logistics, Technology, Cost) means that suppliers do not compete solely on cost. Limited Commitment Zone Firm Zone Time

46 Partners can adapt technology for other markets Slide October 2013 VDL Enabling Technologies Group makes wafer handlers: Knowledge on positioning and temperature management was leveraged for other customers in semiconductors, solar panels and LED lighting. Prodrive makes advanced digital processing and power systems: Technology developed for ASML was re-used in products for medical, consumer electronics and transport markets.

47 Confidential Slide February 2014 What is the role of R&D in the Netherlands?

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