Economic Model Workshop, Philadelphia

Size: px
Start display at page:

Download "Economic Model Workshop, Philadelphia"

Transcription

1 Economic Model Workshop, Philadelphia Denis Fandel, Project Manager, MM&P 1 August 2001

2 Meeting Guidelines Project Mission / Model Overview Early Production Test Program Fundamental Assumption Allocation Process Integrated Model 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 2

3 Setting / keeping the ground rules Focus on the meeting results Treat everyone with respect Differences are valuable - encourage them Criticize ideas not people Everyone participates, no one dominates Encourage all questions/observations No side conversations Use listening skills Seek first to understand then to be understood Ask questions to deepen understanding Keep to the agenda times 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 3

4 What should be discussed Information, models, and data Implications, ideas, questions Areas for industry cooperation What should not be discussed Us versus Them Confidential plans or technology Individual business issues Issues that could be considered Anti-trust 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 4

5 Meeting participants must not make any agreement that restricts output, capacity or the pace of technology innovation No discussion on what any company will do on Prices it will charge, or give any pricing formula Products it will offer unless previously publicly announced Quantities it will produce or min / max capacity it will add No agreement on timing of technology changes Individual companies may state their individual timing to ensure availability of tools and infrastructure May not predicate timing on what competitors are willing to do or agree to 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 5

6 Objective Purpose To educate and train members of the early production team on the functionality and features of ISMT Industry Economic Model Expected Results Comprehensive knowledge and skill in operating ISMT Industry Economic Model for executing scenarios, performing sensitivity analysis and creating reports and graphs. 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 6

7 Model Release (Conditional) - May 31 st, 2001 Agree to participate in EPT program Representative from the IEF members Membership Enrollment / Agreements Actively exercise the model and report on activities Utilize ECONtalk network and participate in Webex meetings Schedule of Key Dates Kick Off Workshop, August 1 st -3 rd, 2001 (2.5 days) Bi-Weekly Work Sessions, August 17 th, 31 st, September 14 th, 2001 Wrap Up Work Session, September 28 th, 2001 (0.5 days) 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 7

8 SEMATECH Team Denis Fandel, Capacity & Productivity ( ) Robert Wright, Building & Equipment ( ) Tim Stanley, Cost Resource Model ( ) Rochelle Remke, User Interface / Tools (rochelle.remke@sematech.org), ( ) Peter Marrone, Administrative Support (peter.marrone@sematech.org), ( ) Neil Gayle, Agere Systems, Supplier Interface (neil.gayle@sematech.org), ( ) Walt Trybula, Lithography Thrust Interface (peter.marrone@sematech.org), ( ) 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 8

9 Early Production Test Team Paul Landler, Consultant ( ) Tom Perry, Agere Systems ( ) Jim Nester / Kelli Polotaye, Silicon Valley Group (nesterj@svg.com), ( ) Kenneth Flamm, University of Texas (kflamm@mail.utexas.edu), ( ) Carlo Guareschi, ST Microelectronics (carlo.guareschi@st.com), ( ) Yon-Chun Chou, National Taiwan University (ychou@ccms.ntu.edu.tw), ( xxxx ) Alan Allan, Intel (alan.k.allan@intel.com), ( ) 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 9

10 Industry Economic Modeling Industry Economic Modeling will assist our member companies and their suppliers as they plan for the future by providing a toolbox to explore technology assumption and business dynamics scenarios. While not a forecasting toolbox, the model will provide unbiased sensitivity analysis as a foundation for building common understanding. 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 10

11 Technology Node Timing, Product Density, Mfg. Process / Tool Needs Yearly Bits, TX Shipments by Technology Node / Product IC Market/Segmentation Model Wafer Starts by Product Type, Fab Type, Technology node Cost / Function Staying on Moore s Law? IC Productivity Model ASSUMED IC Capacity / Fab Model Tools / Material Cost Supplier ROI Model # of Tools by type / technology node Supplier Market / Segmentation Model Tools / Materials Requirements, Revenue by Category 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 11

12 Market forecast in in Si-area per per product family from Semico data Market Elasticity Technology roadmap assumptions and technology distributions Fab Assumptions Equipment assumptions Semi Revenue (Cost-based) Equip Revenue (CRM-based) Fab population Equipment mkt. $ per per function Functions shipped 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 12

13 User Interface Created Access to Assumptions / Data Bases Industry Productivity and Capacity Model (IPCM) Industry Building and Equipment Model (IBEM) Access to Report Generator SEMATECH Productivity Capacity Equipment Summary (SPaCES) SEMATECH Resource Equipment Market Segmentation (STREaMS) Optional Fab - Centric Allocation Process Multi product environment Cost Sensitive Wafer Size Ramp Simplified CRM Created Excel based, interactive with other tools New assumptions added Upgrades Modifiers Beta Test Model 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 13

14 SPaCES / Productivity & Capacity Beta Test Encore Model Upgrades re-enabled with option on range Fab-centric allocation process option added All roadmap scenarios included Revised product groups Redefinition of node ranges Fab aging function Equipment capital escalation factor added STREaMS / Building & Equipment Revised regression factor for calculating wafer cost Coupled silicon, mask and resist to product / process / wafer size All roadmap scenarios included Equipment escalation factor added 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 14

15 Building and Equipment Early Production Test Model Consolidated / Rearranged (50% reduction in space) Expanded to include Processed Wafer Cost Segmented Fixed and Variable Cost Incorporated Packaging / Test uplifts Productivity and Capacity Added fixed and variable cost tables Reordered tables (Capacity / Capital / Cost) Design demand trend modifier Updated density assumptions (nodes pre / post model) Redefined group hierarchy Reconfigured retirement and upgrade windows Instituted auto utilization option 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 15

16 A: 3 year intervals B: 2 year intervals starting in 1997 C: 2000 ITRS (3 year / 2 year / 3 year).5ц.35ц.25ц.18ц.13ц.09ц.065ц A B C /26/2001 6:08 PM j:\stndpres\template\intst.ppt - 16

17 Introduction / Ramp based on productivity Every 9 years with 3 year technology node frequency Modified based on change in technology node pace Cost crossover 2-3 years post introduction 125mm 200mm 300mm 450mm 675mm mm A B C C ITRS /26/2001 6:08 PM j:\stndpres\template\intst.ppt - 17

18 Trends from SEMICO data Wafer size and FAB utilization Technology distribution by product group Retired FABS FAB learning Process flows Equipment and FAB parameters Wafer demand by product group Wafer demand by product group and technology FAB demand by product group and technology New FABS and upgrades optimized for all groups New FABS and upgrades by group and technology Equipment market FAB size and cycle time factors Technology node timing Downgrade FABS Transferred FABS WW manufacturing cost by group Tx area by product group and technology Tx shipments by product group Productivity by group (cost /Tx) 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 18

19 OLE Si Demand LEL Si Demand LEM Si demand by node Retires Upgrades, Builds New Downgrades Converts out Converts out Downgrades Upgrades, Builds New Retires Transfer in Other IC Si demand by node Other S/c Si demand by node Transfer in Retires Upgrades, Builds New Downgrades Scrap Converts out 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 19

20 OLE Si Demand LEL Si Demand LEM Si demand by node Retires, Reserves Upgrades, Builds New Downgrades Converts out Converts out Downgrades Upgrades, Builds New Retires, Reserves Transfer in Other IC Si demand by node Other S/c Si demand by node Transfer in Retires, Reserves Upgrades, Builds New Downgrades Scrap Converts out 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 20

21 Revenue ROI Demand Curve/ Price Sensitivity IC Supply/Segmentation Model IC Productivity FAB / Cost Model Supplier Market / Segmentation Cyclical factors Foundry Analysis Leasing Analysis 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 21

22 Economic Model Workshop, Philadelphia 1 August 2001

23 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 23

24 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 24

25 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 25

26 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 26

27 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 27

28 The worksheets are color-coded. Here is the key: Semico Data Trends Header Variables Semico Data / given information Trends Section Headers Variables Section Dividers The tabs are named according to the product they represent. LEM = Leading Edge Memory LEL = Leading Edge Logic OLE = Other Leading Edge TLE = Total Leading Edge = sum of LEM, LEL, and OLE OIC = Other Integrated Circuits TIC = Total Integrated Circuits = sum of TLE and OIC OSC = Other Semiconductors TSC = Total Semiconductors = sum of TIC and OSC 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 28

29 Row 2, Column B: Scenario in the worksheet Column E : Years in the scenario Row 3, Column A: Products in worksheet group Column E : Cumulative years (+/-) with 1989 as zero Row 4: Wafer diameters introduction year in the scenario Row 5: Technology node introduction year in the scenario Constants: Row1605: Fab Size in wafers / year 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 29

30 Early Production version 2.1 Trend Demand: (Best fit based on observation) Scenario ( A, B, C, CITRS2001) prodcentric Scenario ( A, B, C, CITRS2001) fabcentric True Demand: (Actual / forecast demand for ) Scenario (CITRS2001_SEMICO) prodcentric New macro developed to facilitate data transfer and align to roadmap introduction / life cycle boundaries Scenario (B_CITRS2001_SEMICO demand) prodcentric All with the following allocation process incorporated Upgrades limited to two nodes Retires after the following: LEM/L = 4, OLE = 6, OIC = 8, OSC = 10 Auto-utilization option incorporated 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 30

31 Row # 7-71 Row # Row # Rules File: Row # 7-74 Row # SEMICO product group trends Technology / wafer size distributions by group Fab Capacity Utilization by group Fab Learning by Technology/ wafer size Downgraded Fabs by group, technology, wafer size Row # Row # Row # Row # Row # Wafer area demand by product group Area demand by group, technology, wafer size Fab demand by group, technology, wafer size New, Upgraded Fabs by group, technology, wafer size Converted, Transferred, Retired Fabs by group Row # Row # Row # Row # ITRS product group definitions Wafer demand by group, technology, wafer size Revenue by product group Fab Capacity by group, technology, wafer size Building and Equipment Capital by group, technology, wafer size, Fab type Row # Row # Row # Row # B &E Model: Row # Yield, density by group, technology, wafer size Transistor Shipments and Productivity by group Wafer Mfg Cost by group, technology, wafer size Throughput Learning and Depreciation by group Cost / Capital by group, technology, wafer size 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 31

32 Tool Variables sheet: Rows Equipment Specific Variables (down time, throughput, capital) Global Variables sheet: Rows 1 38 Global Variables (wafer starts, yield, mask data, silicon costs) Product Sheets Rows 116, Calculation of: (per wafer size & tech. node) Total Building Capital Equip Depreciation / wafer Building Depreciation / wafer Variable Wafer Cost Products LEL, LEM, OLE, OIC by technology node and wafer size Product Sheets Rows st column of each node Technology Nodes 500nm - 65nm equipment uses by node/step Product Sheets Cells F 5 - DQ 106 Calculation of: (per each tool) Equipment Count Equipment Capital Equipment Footprint Product Sheets Rows 109, 113, 115 Calculation of: (per wafer size & tech. node) Total Equipment Count Total Equipment Capital Total Equipment Footprint Product Sheets Rows 122, Calculation of: (per wafer size & tech. node) Mask Cost Resist Cost Product Sheets Rows 118 Calculation of: (per wafer size & tech. node) Processed Wafer Cost 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 32

33 Action Item 07/26/2001 6:08 PM j:\stndpres\template\intst.ppt - 33

Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel

Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel Paolo A. Gargini Director Technology Strategy Intel Fellow 1 Agenda 2-year cycle Copy Exactly Conclusions 2 I see no reason

More information

450mm silicon wafers specification challenges. Mike Goldstein Intel Corp.

450mm silicon wafers specification challenges. Mike Goldstein Intel Corp. 450mm silicon wafers specification challenges Mike Goldstein Intel Corp. Outline Background 450mm transition program 450mm silicon evolution Mechanical grade wafers (spec case study) Developmental (test)

More information

DUV. Matthew McLaren Vice President Program Management, DUV. 24 November 2014

DUV. Matthew McLaren Vice President Program Management, DUV. 24 November 2014 DUV Matthew McLaren Vice President Program Management, DUV 24 Forward looking statements This document contains statements relating to certain projections and business trends that are forward-looking,

More information

Lithography. International SEMATECH: A Focus on the Photomask Industry

Lithography. International SEMATECH: A Focus on the Photomask Industry Lithography S P E C I A L International SEMATECH: A Focus on the Photomask Industry by Wally Carpenter, International SEMATECH, Inc. (*IBM Corporation Assignee) It is well known that the semiconductor

More information

Advancing Industry Productivity

Advancing Industry Productivity Advancing Industry Productivity Iddo Hadar Joint Productivity Working Group Session Austin, Texas Thursday, October 12, 2006 F O U N D A T I O N E N G I N E E R I N G G R O U P Safe Harbor Statement This

More information

Semiconductor Industry Perspective

Semiconductor Industry Perspective Semiconductor Industry Perspective National Academy of Engineering Workshop on the Offshoring of Engineering Washington, D.C. October 25, 2006 Dr. Robert Doering Texas Instruments, Inc. A Few Introductory

More information

ISMI Industry Productivity Driver

ISMI Industry Productivity Driver SEMATECH Symposium Japan September 15, 2010 Accelerating Manufacturing Productivity ISMI Industry Productivity Driver Scott Kramer VP Manufacturing Technology SEMATECH Copyright 2010 SEMATECH, Inc. SEMATECH,

More information

Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions.

Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions. Introduction - Chapter 1 Evolution of IC Fabrication 1960 and 1990 integrated t circuits. it Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity

More information

It s Time for 300mm Prime

It s Time for 300mm Prime It s Time for 300mm Prime Iddo Hadar Managing Director, 300mm Prime Program Office SEMI Strategic Business Conference Napa Valley, California Tuesday, April 24, 2007 Safe Harbor Statement This presentation

More information

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004 A Perspective on Semiconductor Equipment R. B. Herring March 4, 2004 Outline Semiconductor Industry Overview of circuit fabrication Semiconductor Equipment Industry Some equipment business strategies Product

More information

The SEMATECH Model: Potential Applications to PV

The SEMATECH Model: Potential Applications to PV Continually cited as the model for a successful industry/government consortium Accelerating the next technology revolution The SEMATECH Model: Potential Applications to PV Dr. Michael R. Polcari President

More information

ASML Market dynamics. Dave Chavoustie EVP Sales Analyst Day, September 30, 2004

ASML Market dynamics. Dave Chavoustie EVP Sales Analyst Day, September 30, 2004 ASML Market dynamics Dave Chavoustie EVP Sales Analyst Day, September 30, 2004 Agenda! Market Overview! Growth Opportunities! 300mm Market! Asia Overview / Slide 2 ASML Unit Market Share Trend 60% 12 &

More information

G450C. Global 450mm Consortium at CNSE. Michael Liehr, General Manager G450C, Vice President for Research

G450C. Global 450mm Consortium at CNSE. Michael Liehr, General Manager G450C, Vice President for Research Global 450mm Consortium at CNSE Michael Liehr, General Manager G450C, Vice President for Research - CNSE Overview - G450C Vision - G450C Mission - Org Structure - Scope - Timeline The Road Ahead for Nano-Fabrication

More information

MAPPER: High throughput Maskless Lithography

MAPPER: High throughput Maskless Lithography MAPPER: High throughput Maskless Lithography Marco Wieland CEA- Leti Alterative Lithography workshop 1 Today s agenda Introduction Applications Qualification of on-tool metrology by in-resist metrology

More information

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09 Study Number MA108-09 August 2009 Copyright Semico Research, 2009. All rights reserved. Reproduction in whole or part is prohibited without permission of Semico. The contents of this report represent

More information

(Complementary E-Beam Lithography)

(Complementary E-Beam Lithography) Extending Optical Lithography with C E B L (Complementary E-Beam Lithography) July 13, 2011 4008 Burton Drive, Santa Clara, CA 95054 Outline Complementary Lithography E-Beam Complements Optical Multibeam

More information

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D 450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D Doug Anberg VP, Technical Marketing Ultratech SOKUDO Lithography Breakfast Forum July 10, 2013 Agenda Next Generation Technology

More information

International SEMATECH Wafer Probe Benchmarking Project WAFER PROBE ROADMAP. Guidance For Wafer Probe R&D Resources Edition

International SEMATECH Wafer Probe Benchmarking Project WAFER PROBE ROADMAP. Guidance For Wafer Probe R&D Resources Edition International SEMATECH Wafer Probe Benchmarking Project WAFER PROBE ROADMAP Guidance For Wafer Probe R&D Resources 2002 Edition Fred Taber, IBM Microelectronics Probe Project Chair Gavin Gibson, Infineon

More information

The future of lithography and its impact on design

The future of lithography and its impact on design The future of lithography and its impact on design Chris Mack www.lithoguru.com 1 Outline History Lessons Moore s Law Dennard Scaling Cost Trends Is Moore s Law Over? Litho scaling? The Design Gap The

More information

The Development of the Semiconductor CVD and ALD Requirement

The Development of the Semiconductor CVD and ALD Requirement The Development of the Semiconductor CVD and ALD Requirement 1 Linx Consulting 1. We create knowledge and develop unique insights at the intersection of electronic thin film processes and the chemicals

More information

Technology Transfers Opportunities, Process and Risk Mitigation. Radhika Srinivasan, Ph.D. IBM

Technology Transfers Opportunities, Process and Risk Mitigation. Radhika Srinivasan, Ph.D. IBM Technology Transfers Opportunities, Process and Risk Mitigation Radhika Srinivasan, Ph.D. IBM Abstract Technology Transfer is quintessential to any technology installation or semiconductor fab bring up.

More information

Intel Technology Journal

Intel Technology Journal Volume 06 Issue 02 Published, May 16, 2002 ISSN 1535766X Intel Technology Journal Semiconductor Technology and Manufacturing The Intel Lithography Roadmap A compiled version of all papers from this issue

More information

In 1951 William Shockley developed the world first junction transistor. One year later Geoffrey W. A. Dummer published the concept of the integrated

In 1951 William Shockley developed the world first junction transistor. One year later Geoffrey W. A. Dummer published the concept of the integrated Objectives History and road map of integrated circuits Application specific integrated circuits Design flow and tasks Electric design automation tools ASIC project MSDAP In 1951 William Shockley developed

More information

AN ANALYSIS: TRADITIONAL SEMICONDUCTOR LITHOGRAPHY VERSUS EMERGING TECHNOLOGY (NANO IMPRINT) Robert L. Wright Kranthi Mitra Adusumilli

AN ANALYSIS: TRADITIONAL SEMICONDUCTOR LITHOGRAPHY VERSUS EMERGING TECHNOLOGY (NANO IMPRINT) Robert L. Wright Kranthi Mitra Adusumilli Proceedings of the 2005 Winter Simulation Conference M. E. Kuhl, N. M. Steiger, F. B. Armstrong, and J. A. Joines, eds. AN ANALYSIS: TRADITIONAL SEMICONDUCTOR LITHOGRAPHY VERSUS EMERGING TECHNOLOGY (NANO

More information

Accelerating Growth and Cost Reduction in the PV Industry

Accelerating Growth and Cost Reduction in the PV Industry Accelerating Growth and Cost Reduction in the PV Industry PV Technology Roadmaps and Industry Standards An Association s Approach Bettina Weiss / SEMI PV Group July 29, 2009 SEMI : The Global Association

More information

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information

Trends and Challenges in VLSI Technology Scaling Towards 100nm

Trends and Challenges in VLSI Technology Scaling Towards 100nm Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends

More information

4Q02 Update: Semiconductor Capacity Still on Hold

4Q02 Update: Semiconductor Capacity Still on Hold Research Brief 4Q02 Update: Semiconductor Capacity Still on Hold Abstract: Semiconductor capacity expansions have gone into a hold mode as soft semiconductor demand drops utilization rates lower. Further

More information

Lithography in our Connected World

Lithography in our Connected World Lithography in our Connected World SEMI Austin Spring Forum TOP PAN P R INTING CO., LTD MATER IAL SOLUTIONS DIVISION Toppan Printing Co., LTD A Broad-Based Global Printing Company Foundation: January 17,

More information

Photoresists & Ancillaries. Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report

Photoresists & Ancillaries. Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report 2018-19 Photoresists & Ancillaries Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report Prepared by Ed Korczynski Reviewed and Edited by Lita Shon-Roy TECHCET CA LLC PO Box 3814

More information

Intel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors

Intel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors Intel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors Mark Bohr Intel Senior Fellow Logic Technology Development Kaizad Mistry 45 nm Program Manager Logic Technology Development

More information

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration Intel 1 What are We Announcing? Intel has fabricated fully-functional

More information

1 Digital EE141 Integrated Circuits 2nd Introduction

1 Digital EE141 Integrated Circuits 2nd Introduction Digital Integrated Circuits Introduction 1 What is this lecture about? Introduction to digital integrated circuits + low power circuits Issues in digital design The CMOS inverter Combinational logic structures

More information

Scaling of Semiconductor Integrated Circuits and EUV Lithography

Scaling of Semiconductor Integrated Circuits and EUV Lithography Scaling of Semiconductor Integrated Circuits and EUV Lithography ( 半導体集積回路の微細化と EUV リソグラフィー ) December 13, 2016 EIDEC (Emerging nano process Infrastructure Development Center, Inc.) Hidemi Ishiuchi 1 OUTLINE

More information

Nikon Medium Term Management Plan

Nikon Medium Term Management Plan NIKON CORPORATION Mar.30,2006 Nikon Medium Term Management Plan March 30, 2006 NIKON CORPORATION This presentation contains forward-looking statements with respect to future results, performance and achievements

More information

Enabling Semiconductor Innovation and Growth

Enabling Semiconductor Innovation and Growth Enabling Semiconductor Innovation and Growth EUV lithography drives Moore s law well into the next decade BAML 2018 APAC TMT Conference Taipei, Taiwan Craig De Young Vice President IR - Asia IR March 14,

More information

2010 IRI Annual Meeting R&D in Transition

2010 IRI Annual Meeting R&D in Transition 2010 IRI Annual Meeting R&D in Transition U.S. Semiconductor R&D in Transition Dr. Peter J. Zdebel Senior VP and CTO ON Semiconductor May 4, 2010 Some Semiconductor Industry Facts Founded in the U.S. approximately

More information

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group Multiple Patterning for Immersion Extension and EUV Insertion Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group Abstract Multiple Patterning for Immersion Extension and

More information

W ith development risk fully borne by the equipment industry and a two-year delay in the main

W ith development risk fully borne by the equipment industry and a two-year delay in the main Page 1 of 5 Economic Challenges and Opportunities in the 300 mm Transition Iddo Hadar, Jaim Nulman, Kunio Achiwa, and Oded Turbahn, Applied Materials Inc. -- 10/1/1998 Semiconductor International W ith

More information

Commercializing Innovation:

Commercializing Innovation: 2011 International Symposium on Lithography Extensions: Oct 2011 Commercializing Innovation: Lessons from the lithography cycles Risto Puhakka This report has been reproduced for 2011 International Symposium

More information

HOW TO CONTINUE COST SCALING. Hans Lebon

HOW TO CONTINUE COST SCALING. Hans Lebon HOW TO CONTINUE COST SCALING Hans Lebon OUTLINE Scaling & Scaling Challenges Imec Technology Roadmap Wafer size scaling : 450 mm 2 COST SCALING IMPROVED PERFORMANCE 3 GLOBAL TRAFFIC FORECAST Cloud Traffic

More information

The Road to 450 mm Semiconductor Wafers Ira Feldman

The Road to 450 mm Semiconductor Wafers Ira Feldman The Road to 450 mm Semiconductor Wafers Ira Feldman Feldman Engineering Corp. Why 450 mm Wafers? Technical Challenges Economic Challenges Solutions Summary Overview 2 the number of transistors on a chip

More information

Applications for Mask-less E-Beam Lithography between R&D and Manufacturing

Applications for Mask-less E-Beam Lithography between R&D and Manufacturing Applications for Mask-less E-Beam Lithography between R&D and Manufacturing May 24, 2006 Lithography Forum Johannes Kretz Table of Contents E-Beam Lithography at Qimonda in Dresden Project Environment

More information

THE WAFER FAB CLEANS IN SEMICONDUCTOR INDUSTRY FROM A MATERIALS SUPPLIER PERSPECTIVE

THE WAFER FAB CLEANS IN SEMICONDUCTOR INDUSTRY FROM A MATERIALS SUPPLIER PERSPECTIVE THE WAFER FAB CLEANS IN SEMICONDUCTOR INDUSTRY FROM A MATERIALS SUPPLIER PERSPECTIVE Tianniu Rick Chen, Ph.D. General Manager SP&C Business (Surface Preparation & Cleans) OUTLINE Market drivers and challenges

More information

EUV Supporting Moore s Law

EUV Supporting Moore s Law EUV Supporting Moore s Law Marcel Kemp Director Investor Relations - Europe DB 2014 TMT Conference London September 4, 2014 Forward looking statements This document contains statements relating to certain

More information

CMP: Where have we been and where are we headed next? Robert L. Rhoades, Ph.D. NCCAVS CMPUG Meeting at Semicon West San Francisco, July 10, 2013

CMP: Where have we been and where are we headed next? Robert L. Rhoades, Ph.D. NCCAVS CMPUG Meeting at Semicon West San Francisco, July 10, 2013 CMP: Where have we been and where are we headed next? Robert L. Rhoades, Ph.D. NCCAVS CMPUG Meeting at Semicon West San Francisco, July 10, 2013 Outline Where have we been? Semiconductor Industry Birth

More information

Common Development Topics for Semiconductor Manufacturers and their Suppliers in Germany

Common Development Topics for Semiconductor Manufacturers and their Suppliers in Germany Common Development Topics for Semiconductor Manufacturers and their Suppliers in Germany SEMICON Europa 2013 TechARENA 1: Secondary Equipment Session Contact: Dr.-Ing. Martin Schellenberger, Fraunhofer

More information

ISSCC 2003 / SESSION 1 / PLENARY / 1.1

ISSCC 2003 / SESSION 1 / PLENARY / 1.1 ISSCC 2003 / SESSION 1 / PLENARY / 1.1 1.1 No Exponential is Forever: But Forever Can Be Delayed! Gordon E. Moore Intel Corporation Over the last fifty years, the solid-state-circuits industry has grown

More information

Doug Dunn ASML President and Chief Executive Officer Deutsche Bank Conference London, England September 19, / Slide 1

Doug Dunn ASML President and Chief Executive Officer Deutsche Bank Conference London, England September 19, / Slide 1 Doug Dunn ASML President and Chief Executive Officer Deutsche Bank Conference London, England September 19, 2003 / Slide 1 Safe Harbor Safe Harbor Statement under the U.S. Private Securities Litigation

More information

Introduction to VLSI ASIC Design and Technology

Introduction to VLSI ASIC Design and Technology Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics

More information

The European Semiconductor industry: 2005 Competitiveness Report. DG Enterprise

The European Semiconductor industry: 2005 Competitiveness Report. DG Enterprise The European Semiconductor industry: 2005 Competitiveness Report DG Enterprise EU presentation, Brussels, September 1, 2005 1 EU presentation, Brussels, September 1, 2005 2 EU presentation, Brussels, September

More information

ISMI 450mm Transition Program

ISMI 450mm Transition Program SEMATECH Symposium Taiwan September 7, 2010 Accelerating Manufacturing Productivity ISMI 450mm Transition Program Scott Kramer VP Manufacturing Technology SEMATECH Copyright 2010 SEMATECH, Inc. SEMATECH,

More information

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm SEMICON West, San Francisco July 14-18, 2008 Slide 1 The immersion pool becomes an ocean

More information

Flexline - A Flexible Manufacturing Method for Wafer Level Packages (Extended Abstract)

Flexline - A Flexible Manufacturing Method for Wafer Level Packages (Extended Abstract) Flexline - A Flexible Manufacturing Method for Wafer Level Packages (Extended Abstract) by Tom Strothmann, *Damien Pricolo, **Seung Wook Yoon, **Yaojian Lin STATS ChipPAC Inc.1711 W Greentree Drive Tempe,

More information

Proceedings. BiTS Shanghai October 21, Archive - Session BiTS Workshop Image: Zhu Difeng/Dollar Photo Club

Proceedings. BiTS Shanghai October 21, Archive - Session BiTS Workshop Image: Zhu Difeng/Dollar Photo Club Proceedings Archive - Session 1 2015 BiTS Workshop Image: Zhu Difeng/Dollar Photo Club Proceedings With Thanks to Our Sponsors! Premier Honored Distinguished Publication Sponsor 2 Proceedings Presentation

More information

Copyright 2003 by the Society of Photo-Optical Instrumentation Engineers.

Copyright 2003 by the Society of Photo-Optical Instrumentation Engineers. Copyright 2003 by the Society of Photo-Optical Instrumentation Engineers. This paper was published in the proceedings of Optical Microlithography XVI, SPIE Vol. 5040, pp. xxi-xxxi. It is made available

More information

Burn-in & Test Socket Workshop

Burn-in & Test Socket Workshop Burn-in & Test Socket Workshop IEEE March 3-6, 2002 Hilton Phoenix East/Mesa Hotel Mesa, Arizona IEEE COMPUTER SOCIETY Sponsored By The IEEE Computer Society Test Technology Technical Council COPYRIGHT

More information

NO COST APPLICATIONS FOR ASSEMBLY CYCLE TIME REDUCTION

NO COST APPLICATIONS FOR ASSEMBLY CYCLE TIME REDUCTION NO COST APPLICATIONS FOR ASSEMBLY CYCLE TIME REDUCTION Steven Brown, Joerg Domaschke, and Franz Leibl Siemens AG, HL MS Balanstrasse 73 Munich 81541, Germany email: steven.brown@siemens-scg.com KEY WORDS

More information

Recent Trends in Semiconductor IC Device Manufacturing

Recent Trends in Semiconductor IC Device Manufacturing Recent Trends in Semiconductor IC Device Manufacturing August 2007 Dr. Stephen Daniels Executive Director National Centre for Plasma Moore s Law Moore s First Law Chip Density will double ever 18months.

More information

WHITE PAPER CIRCUIT LEVEL AGING SIMULATIONS PREDICT THE LONG-TERM BEHAVIOR OF ICS

WHITE PAPER CIRCUIT LEVEL AGING SIMULATIONS PREDICT THE LONG-TERM BEHAVIOR OF ICS WHITE PAPER CIRCUIT LEVEL AGING SIMULATIONS PREDICT THE LONG-TERM BEHAVIOR OF ICS HOW TO MINIMIZE DESIGN MARGINS WITH ACCURATE ADVANCED TRANSISTOR DEGRADATION MODELS Reliability is a major criterion for

More information

MIDTERM REVIEW INDU 421 (Fall 2013)

MIDTERM REVIEW INDU 421 (Fall 2013) MIDTERM REVIEW INDU 421 (Fall 2013) Problem #1: A job shop has received on order for high-precision formed parts. The cost of producing each part is estimated to be $65,000. The customer requires that

More information

Electron Multi-Beam Technology for Mask and Wafer Direct Write. Elmar Platzgummer IMS Nanofabrication AG

Electron Multi-Beam Technology for Mask and Wafer Direct Write. Elmar Platzgummer IMS Nanofabrication AG Electron Multi-Beam Technology for Mask and Wafer Direct Write Elmar Platzgummer IMS Nanofabrication AG Contents 2 Motivation for Multi-Beam Mask Writer (MBMW) MBMW Tool Principles and Architecture MBMW

More information

Beyond Moore the challenge for Europe

Beyond Moore the challenge for Europe Beyond Moore the challenge for Europe Dr. Alfred J. van Roosmalen Vice-President Business Development, NXP Semiconductors Company member of MEDEA+/CATRENE/AENEAS/Point-One FIT-IT 08 Spring Research Wien,

More information

Comparison of Drilling Rates and Tolerances of Laser-Drilled holes in Silicon Nitride and Polyimide Vertical Probe Cards

Comparison of Drilling Rates and Tolerances of Laser-Drilled holes in Silicon Nitride and Polyimide Vertical Probe Cards Dr. Alan Ferguson Oxford Lasers Comparison of Drilling Rates and Tolerances of Laser-Drilled holes in Silicon Nitride and Polyimide Vertical Probe Cards June 8-11, 8 2008 San Diego, CA USA Overview Introduction

More information

A Semiconductor Manufacturers Perspective on Obsolescence and Counterfeiting

A Semiconductor Manufacturers Perspective on Obsolescence and Counterfeiting A Semiconductor Manufacturers Perspective on Obsolescence and Counterfeiting Peter Marston Business Development and Technical Consultant IIOM Conference June 2015 Topics Semiconductor Manufacturing - Historical

More information

The Future of Packaging ~ Advanced System Integration

The Future of Packaging ~ Advanced System Integration The Future of Packaging ~ Advanced System Integration Enabling a Microelectronic World R. Huemoeller SVP, Adv. Product / Platform Develop June 2013 Product Segments End Market % Share Summary 2 New Product

More information

Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference

Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference Craig De Young Vice President Investor Relations Taipei, Taiwan March 12, 2013 Forward looking statements Slide 2 Safe Harbor Statement

More information

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978)

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978) IC Knowledge LLC, PO Box 20, Georgetown, MA 01833 www.icknowledge.com Ph: (978) 352 7610, Fx: (978) 352 3870 Linx Consulting, PO Box 384, Mendon, MA 01756 0384 www.linxconsulting.com Ph: (617) 273 8837

More information

Competitive in Mainstream Products

Competitive in Mainstream Products Competitive in Mainstream Products Bert Koek VP, Business Unit manager 300mm Fabs Analyst Day 20 September 2005 ASML Competitive in mainstream products Introduction Market share Device layers critical

More information

Testing of Complex Digital Chips. Juri Schmidt Advanced Seminar

Testing of Complex Digital Chips. Juri Schmidt Advanced Seminar Testing of Complex Digital Chips Juri Schmidt Advanced Seminar - 11.02.2013 Outline Motivation Why testing is necessary Background Chip manufacturing Yield Reasons for bad Chips Design for Testability

More information

WLP Probing Technology Opportunity and Challenge. Clark Liu

WLP Probing Technology Opportunity and Challenge. Clark Liu WLP Probing Technology Opportunity and Challenge Founded Capital PTI Group Overview : May/15/97 : USD 246 Millions PTI HQ Total Assets : USD 2.2B Employees Major Services : 11,100 (Greatek included) :

More information

Public. Introduction to ASML. Ron Kool. SVP Corporate Strategy and Marketing. March-2015 Veldhoven

Public. Introduction to ASML. Ron Kool. SVP Corporate Strategy and Marketing. March-2015 Veldhoven Public Introduction to ASML Ron Kool SVP Corporate Strategy and Marketing March-2015 Veldhoven 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

More information

Mask magnification at the 45-nm node and beyond

Mask magnification at the 45-nm node and beyond Mask magnification at the 45-nm node and beyond Summary report from the Mask Magnification Working Group Scott Hector*, Mask Strategy Program Manager, ISMT Mask Magnification Working Group January 29,

More information

ITRS Update (and the European situation) Mart Graef Delft University of Technology

ITRS Update (and the European situation) Mart Graef Delft University of Technology ITRS Update (and the European situation) Mart Graef Delft University of Technology Overview Roadmapping: Moore s Law & More than Moore Europe and the Roadmap Beyond CMOS: Nano-Tec Infrastructures: ENI2

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS LUC VAN DEN HOVE President & CEO imec OUTLINE! Industry drivers! Roadmap extension! Lithography options! Innovation through global collaboration

More information

EVCA Strategic Priorities

EVCA Strategic Priorities EVCA Strategic Priorities EVCA Strategic Priorities The following document identifies the strategic priorities for the European Private Equity and Venture Capital Association (EVCA) over the next three

More information

Toolbox for Renewable Energy Tariff Design in West African Countries

Toolbox for Renewable Energy Tariff Design in West African Countries Toolbox for Renewable Energy Tariff Design in West African Countries Abuja, 20-21 July 2017 Abuja, 20-21 July 2017 page 1 Part A Welcome and Introduction Abuja, 20-21 July 2017 Abuja, 20-21 July 2017 page

More information

Multi-Family Council - Blue

Multi-Family Council - Blue DOWNLOAD THE ULI EVENTS APP FALL MEETING Optimize your experience at ULI meetings and conferences with the free ULI Events app Plan your schedule Connect with other leaders at the Fall meeting Find nearby

More information

UNCLASSIFIED. R-1 ITEM NOMENCLATURE PE S: Microelectronics Technology Development and Support (DMEA) FY 2013 OCO

UNCLASSIFIED. R-1 ITEM NOMENCLATURE PE S: Microelectronics Technology Development and Support (DMEA) FY 2013 OCO Exhibit R-2, RDT&E Budget Item Justification: PB 2013 Defense Logistics Agency DATE: February 2012 COST ($ in Millions) FY 2011 FY 2012 Base OCO Total FY 2014 FY 2015 FY 2016 FY 2017 Defense Logistics

More information

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING Henry H. Utsunomiya Interconnection Technologies, Inc. Suwa City, Nagano Prefecture, Japan henryutsunomiya@mac.com ABSTRACT This presentation will outline

More information

INSPECTION AND REVIEW PORTFOLIO FOR 3D FUTURE

INSPECTION AND REVIEW PORTFOLIO FOR 3D FUTURE INSPECTION AND REVIEW PORTFOLIO FOR 3D FUTURE This week announced updates to four systems the 2920 Series, Puma 9850, Surfscan SP5 and edr-7110 intended for defect inspection and review of 16/14nm node

More information

ASICs Concept to Product

ASICs Concept to Product ASICs Concept to Product Synopsis This course is aimed to provide an opportunity for the participant to acquire comprehensive technical and business insight into the ASIC world. As most of these aspects

More information

TRUST in Integrated Circuits Program

TRUST in Integrated Circuits Program TRUST in Integrated Circuits Program Briefing to Industry Mr. Brian Sharkey i_sw Corp 26 March 2007 Agenda 0800-0815 0815 Introductions and Agenda 0815-0900 0900 Technical Objectives of the TRUST Program

More information

Market and technology trends in advanced packaging

Market and technology trends in advanced packaging Close Market and technology trends in advanced packaging Executive OVERVIEW Recent advances in device miniaturization trends have placed stringent requirements for all aspects of product manufacturing.

More information

21 st Annual Needham Growth Conference

21 st Annual Needham Growth Conference 21 st Annual Needham Growth Conference Investor Presentation January 15, 2019 Safe Harbor Statement The information contained in and discussed during this presentation may include forward-looking statements

More information

International Technology Roadmap for Semiconductors. Dave Armstrong Advantest Ira Feldman Feldman Engineering Marc Loranger - FormFactor

International Technology Roadmap for Semiconductors. Dave Armstrong Advantest Ira Feldman Feldman Engineering Marc Loranger - FormFactor International Technology Roadmap for Semiconductors Dave Armstrong Advantest Ira Feldman Feldman Engineering Marc - FormFactor Who are we? Why a roadmap? What is the purpose? Example Trends How can you

More information

Wide Band-Gap Semiconductors GaN & SiC

Wide Band-Gap Semiconductors GaN & SiC Who What Where When Why Wide Band-Gap Semiconductors GaN & SiC Your 2015 APEC Rap Session - 17 of March 2015 Charlotte, NC Wide Band Gap - Rap Session 2015 Schedule Panelists introduction Introduction

More information

Limitations and Challenges to Meet Moore's Law

Limitations and Challenges to Meet Moore's Law Limitations and Challenges to Meet Moore's Law Sept 10, 2015 Sung Kim sung_kim@amat.com State of the art: cleanroom toolsets metrology analysis module development test & reliability Introduction Why do

More information

2015 ITRS/RC Summer Meeting

2015 ITRS/RC Summer Meeting 2015 ITRS/RC Summer Meeting July 11 and 12, Stanford University, CISX 101 July 11 Time Duration Presentation Title Speaker Affiliation 7:30 am Breakfast 8:00 am 60 min Introduction Paolo Gargini ITRS 9:00am

More information

Commodity Management in the Department of Defense

Commodity Management in the Department of Defense 0 DMSMS Workshop Commodity Management in the Department of Defense Microelectronics Commodity San Antonio, TX December, 2005 1 Contents Introduction Issues and trends (DoD vs. Industry) Commodity overview

More information

GSEF 2019 Advisory Board

GSEF 2019 Advisory Board GSEF 2019 Advisory Board Ralph Lauxmann, Senior Vice President Systems & Technology, Continental Automotive Hans Adlkofer, Vice President Systems Group, The Automotive Division, Infineon Technologies Hai

More information

Specialization in Microelectronics. Wang Qijie Nanyang Assistant Professor in EEE March 8, 2013

Specialization in Microelectronics. Wang Qijie Nanyang Assistant Professor in EEE March 8, 2013 Specialization in Microelectronics Wang Qijie Nanyang Assistant Professor in EEE qjwang@ntu.edu.sg March 8, 2013 Electronic Engineering Option Microelectronics What is it about? Study of semiconductor

More information

THE CCD RIDDLE REVISTED: SIGNAL VERSUS TIME LINEAR SIGNAL VERSUS VARIANCE NON-LINEAR

THE CCD RIDDLE REVISTED: SIGNAL VERSUS TIME LINEAR SIGNAL VERSUS VARIANCE NON-LINEAR THE CCD RIDDLE REVISTED: SIGNAL VERSUS TIME LINEAR SIGNAL VERSUS VARIANCE NON-LINEAR Mark Downing 1, Peter Sinclaire 1. 1 ESO, Karl Schwartzschild Strasse-2, 85748 Munich, Germany. ABSTRACT The photon

More information

International Technology Roadmap for Semiconductors. Dave Armstrong Advantest Ira Feldman Feldman Engineering Marc Loranger FormFactor

International Technology Roadmap for Semiconductors. Dave Armstrong Advantest Ira Feldman Feldman Engineering Marc Loranger FormFactor International Technology Roadmap for Semiconductors Dave Armstrong Advantest Ira Feldman Feldman Engineering Marc Loranger FormFactor Who are we? Why a roadmap? What is the purpose? Example Trends How

More information

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information

Story. Cover. R e d e fining Moore s Law

Story. Cover. R e d e fining Moore s Law Cover Story R e d e fining Moore s Law Chris A. Mack, KLA-Tencor Corporation The economic drivers of Moore s Law can be divided into push drivers and pull drivers. Push drivers are the technology innovations

More information

Manufacturing Readiness Assessment Overview

Manufacturing Readiness Assessment Overview Manufacturing Readiness Assessment Overview Integrity Service Excellence Jim Morgan AFRL/RXMS Air Force Research Lab 1 Overview What is a Manufacturing Readiness Assessment (MRA)? Why Manufacturing Readiness?

More information

1Q04 Update: Silicon Demand Will Move to a Full Recovery

1Q04 Update: Silicon Demand Will Move to a Full Recovery Gartner Dataquest Alert 1Q04 Update: Silicon Demand Will Move to a Full Recovery Our latest silicon demand forecast indicates that wafer demand in 2003 will increase 9 percent over 2002. While the forecast

More information

Announcements. Advanced Digital Integrated Circuits. Project proposals due today. Homework 1. Lecture 8: Gate delays,

Announcements. Advanced Digital Integrated Circuits. Project proposals due today. Homework 1. Lecture 8: Gate delays, EE4 - Spring 008 Advanced Digital Integrated Circuits Lecture 8: Gate delays, Variability Announcements Project proposals due today Title Team members ½ page ~5 references Post it on your EECS web page

More information